Texas Instruments Corporation

Nippon Paper Industries Co., Ltd.

Yuji Ozawa

Frederic Boutaud

Shigeshi Abiko

Takashi Ochi

Tadashi Saito

Koichi Yanai

Akinobu Chatani

Dai Nagahara

Toshikazu Teramasa

Kunio Takebayashi

Masashi Seki

A method for manufacturing an inkjet recording medium comprising the steps of: applying a coating color containing a pigment and a binder as major components to at least one side of a base material using a transfer roll coater, subsequently drying coating layer to form an ink absorbing layer, wherein Hercules viscosity of coating color is 5 m Pa&#xb7;s to 30 m Pa&#xb7;s and pigment contains a synthetic silica having an oil absorption of 90 ml/10 g to 200 ml/100 g, a BET specific surface area of 45 m/g to 200 m/g and an average particle diameter of 1.0 &#x3bc;m to 3.0 &#x3bc;m and/or a precipitated calcium carbonate-silica composite having an oil absorption of 100 ml/10 g to 250 ml/100 g, a BET specific surface area of 5 m/g to 150 m/g and an average particle diameter of 1.0 &#x3bc;m to 10 &#x3bc;m.

Process for producing inkjet recording medium

An inkjet recording medium comprising at least one ink receiving layer on a support, wherein the ink receiving layer which is the outermost layer comprises a pigment and an aqueous polyurethane resin as principal components, the proportion of said aqueous polyurethane resin relative to said pigment in the ink receiving layer which is the outermost layer is 5-80 wt %, said aqueous polyurethane resin is formed by reaction of an active hydrogen compound and an aliphatic and/or alicyclic polyisocyanate compound, said active hydrogen compound contains 40-80 wt % of a polyether polyol compound having a number average molecular weight of 500-3000, and the minimum film-forming temperature of said aqueous polyurethane resin is &#x2212;10-50 degree C.

Inkjet recording medium

An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt. The zero detection circuit also deactivates the loop-end control signal for the number of clock cycles equivalent to the depth of the prefetch pipeline during the final repeat loop iteration(s) so that a loop with a block size less than or equal to the depth of the prefetch pipeline can be repeated the correct number of times.

Address generating circuit for block repeat addressing for a pipelined

An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is positive, an index generating circuit subtracts the sum of the index and step value from a block size of a memory region. Depending on the subtraction result, an output which is either the sum of the index and step value or the subtraction result is provided as a new index. When the step value is negative, the index and step value are added. Depending on the addition result, an output which is either the sum of the index, step value, and capacity of the memory region or the addition result is provided as a new index. A bit multiplexer 314 generates the next address from the new index and an address.

Address generating circuit for generating addresses separated by a

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Tokyo, Japan

Yuji Ozawa