Fujitsu Corporation

Yuji Obana

Hideaki Mochizuki

Hideo Abe

Hiromichi Makishima

Masanori Hiramoto

Masayuki Tanaka

Nobukazu Koizumi

Kazuhiko Hatae

Hiroyuki Asano

Hiroyuki Kitajima

Noriyasu Nakayama

Wataru Odashima

Hidetaka Kawahara

Kazumasa Mikami

Ichiro Yokokura

Shingo Hotta

Toshiaki Ookubo

A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.

Transmission device

An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Optical digital coherent receiver

In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of dataclock prior to and a head bit of dataclock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.

Jitter correction method and circuit

A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion

An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.

Cell bridge apparatus and cell bridging method as well as information transmission system having cell bridge apparatus

Digital signal multiplexing apparatus and demultiplexing apparatus

A complex multiplexer/demultiplexer apparatus which converts input low order group data signals to middle order group data signals and multiplexes them to high order group data signals and converts high order group data signals to middle order group data signals and demultiplexes them to low order group data signals, wherein a plurality of low order group channels are processed by multiplexing and demultiplexing at a second clock bit synchronized with a first clock on the high order group side, the second clock including empty bits, and the bit rate being set lower than the first clock, and signal speeds between each of first multiplexers and a second multiplexer and between a first demultiplexer and each of second demultiplexers are converted by insertion and deletion of the empty bits which may have inserted therein additional information.

Complex multiplexer/demultiplexer apparatus

Growing community of inventors

Kawasaki, Japan

Yuji Obana