Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Yuji Nakai

Tomohiro Kimura

Naoki Kuroda

Kenichiro Hayashi

Sadashi Kageyama

Akihiro Furuta

Hiroki Furukawa

Akira Kisoda

Takehiro Kamada

Shunsuke Sakai

Takashi Kakemizu

A transmission method of a digital broadcast, which is compatible with a DVB-T terrestrial digital broadcast system in Europe, saves a battery in a mobile terminal. Superframes in DVB-T are divided into units each including plural symbols so that an integer number of TS packets can be carried in each slot. At least one slot is used to transmit one service. Energy dispersion, Reed-Solomon coding, byte interleaving, convolutional coding, and time interleaving are applied to each service. When services for mobile terminal reception and services for fixed terminals are transmitted as the provided services, null packets may be transmitted before and after the slot carrying the mobile receiver service so that the fixed reception service and the mobile reception services are not mixed.

OFDM signal transmission method, transmission apparatus, and reception apparatus

A receiving apparatus () includes demodulation parts () for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part () for outputting, to an A/V decoder (), the two timing clocks from the demodulation parts () as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts (), and a multiplexing part () for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder (). The A/V decoder () receives the multiplexed data and timing clocks from the receiving apparatus () to process the video/audio signals of each broadcast.

Receiving apparatus, receiving system using same, and receiving method thereof

Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

Semiconductor integrated circuit device

A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits

In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST ) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST ). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST , ST ).

Encoding rate detection method and encoding rate detection device

In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a RAM by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter

In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

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Osaka, Japan

Yuji Nakai