Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Yuji Nakagawa

Hajime Sato

Satoru Kawamoto

Hiroyuki Tanaka

A receiving circuit includes: a terminating resistor to set a terminating level of a transmission line for transmitting a reception signal including a signal having a first level indicating a preamble; a detection circuit to detect whether a level of the transmission line is the first level or a second level; and an adjustment circuit to adjust a resistance of the terminating resistor, the adjustment circuit adjusting the resistance of the terminating resistor to a value such that the detection circuit detects the level of the transmission line as the second level when a data request is output to a transmitting side.

Receiving circuit and methods for controlling and testing the same

A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Semiconductor device, memory system and control method of the semiconductor device

A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

Semiconductor memory device and refresh method for the same

Disclosed is a semiconductor memory device which shortens an external access time when there is contention between an external access and an internal access. The semiconductor memory device includes an arbiter which receives a first entry signal for entering a first access mode (external access) and a second entry signal for entering a second access mode (internal access) and determines priority of the first and second access modes in accordance with an order of receipt of the first and second entry signals. The arbiter sequentially generates a first mode trigger signal corresponding to the first entry signal and a second mode trigger signal corresponding to the second entry signal in accordance with the determined priority. The arbiter executes the first access mode by priority over the second access mode when the arbiter is supplied with the first entry signal with a predetermined period after the second access mode has been determined to have priority.

Memory device and method for arbitrating internal and external access

A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.

Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device

A semiconductor memory device for easily and accurately evaluating a device. The memory device has a first access mode and a second access mode. The memory device includes an entry signal generation circuit to synthesize input signals and generate a first entry signal used to enter the first access mode. A control circuit generates a first mode trigger signal in response to the first entry signal. The control circuit also receives a second entry signal used to enter the second access mode and generates a second mode trigger signal in response to the second entry signal. The entry signal generation circuit logically synthesizes the input signals in a selective manner in accordance with a selection control signal to generate the first entry signal.

Growing community of inventors

Kasugai, Japan

Yuji Nakagawa