Mitsubishi Electric Corporation

Sumco Corporation

Yuji Miyazaki

Yasushi Nakayama

Yoshiko Obiraki

Hiroshi Nakatake

Yasutaka Shimizu

Takeshi Horiguchi

Mituharu Tabata

Tatsunori Yanagimoto

Kazuya Okada

Hidetoshi Nakanishi

Provided is a method of double-side polishing a wafer by which variations of the GBIR values of polished wafers between batches can be reduced. In the method of double-side polishing a wafer, a current batch includes measuring the center thickness of the wafer before polishing (S100); setting a target GBIR value within a predetermined range (S110); calculating a polishing time of the current batch based on Formula (1) (S120); and polishing both surfaces of the wafer for the calculated polishing time (S130).Polishing time of current batch=polishing time of previous batch+&#xd7;(center thickness of wafer before polishing in previous batch&#x2212;center thickness of wafer before polishing in current batch)+&#xd7;(GBIR value of wafer after polishing in previous batch&#x2212;target GBIR value)+&#x2003;&#x2003;(1),

Method of double-side polishing wafer

There are provided a small-sized power semiconductor module and a small-sized power conversion device capable of reducing ringing voltage. A power semiconductor module includes: a positive electrode-side switching element and a positive electrode-side freewheeling diode corresponding to a positive electrode-side power semiconductor element; a negative electrode-side switching element and a negative electrode-side freewheeling diode corresponding to a negative electrode-side power semiconductor element; a positive electrode conductor pattern; a negative electrode conductor pattern; an AC electrode pattern; and a snubber substrate including an insulating substrate having a snubber circuit formed thereon. The snubber substrate includes the insulating substrate and the at least one snubber circuit arranged on the insulating substrate. The snubber substrate is arranged on at least one of the positive electrode conductor pattern, the negative electrode conductor pattern and the AC electrode pattern.

Power semiconductor module and power conversion device

The object is to provide a technology for enabling detection of the voltage resistance in an assembled snubber substrate. A semiconductor device includes: a snubber substrate fixed to a base while being spaced from a p electrode and an n electrode; a snubber circuit disposed on the snubber substrate and electrically connected to the p electrode and the n electrode; and a semiconductor element electrically connected to the snubber circuit. The base includes an insulating component insulating the p electrode, the n electrode, and the snubber substrate from one another.

Semiconductor device and method for manufacturing the same

Examples of a semiconductor device includes a first switching element including a first gate, a first source connected to a common terminal via a first connection line, and a first drain, a second switching element including a second gate, a second source that is connected to the first source via a second connection line and connected to the common terminal via the first connection line and the second connection line, a first capacitor for connecting the first source and a high voltage side of a power supply, a first circuit element having first end connected between the high voltage side of the power supply and the first capacitor, and a second capacitor for connecting the second source and second end of the first circuit element.

Semiconductor device

A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; a positive electrode terminal, a negative electrode terminal, and an AC terminal that are connected to each of the circuit blocks; and wiring patterns that connect the self-arc-extinguishing type semiconductor elements of the circuit blocks to the positive electrode terminal, the negative electrode terminal, and the AC terminal, wherein the circuit block is plural in number; the positive electrode terminal, the negative electrode terminal, and the AC terminal are each disposed to be plural in number corresponding to the circuit blocks; and the positive electrode terminals and the negative electrode terminals are closely disposed.

A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; first and second positive electrode terminals, first and second negative electrode terminals, and first and second AC terminals. Further, there are first and second wiring patterns that connect the self-arc-extinguishing type semiconductor elements to the DC and AC terminals. The outline of the power semiconductor module has a substantially quadrangular surface.

A driving circuit of the present invention drives a switching element connected to a main current circuit. The driving circuit includes a driving potion applying on/off-voltage to a gate of the switching element, a common inductor disposed in an interconnection part commonly connected to the driving circuit and a source side of the switching element in a loop formed of the main current circuit and the switching element, and a capacitor connected between the gate side and the source side on the driving portion side with respect to the common inductor.

Driving circuit and semiconductor device

A semiconductor device includes an insulating substrate, a metal pattern formed on the insulating substrate, a power terminal bonded onto the metal pattern, and a plurality of power chips bonded onto the metal pattern. The plurality of power chips are all separated from the power terminal by a distance sufficient to thermally isolate the plurality of power chips from the power terminal.

High power semiconductor device

A drive circuit for an IGBT includes an H-bridge circuit using first to fourth switch elements. When a control unit receives a command for changing the IGBT from an on state to an off state, it switches states of the first to fourth switch elements from a first state in which the first and fourth switch elements are in an on state and the second and third switch elements are in an off state to a second state in which the first and fourth switch elements are in the off state and the second and third switch elements are in the on state. This structure of the drive circuit can apply a reverse bias to the IGBT from a single power supply.

Growing community of inventors

Tokyo, Japan

Yuji Miyazaki