Rohm Co., Ltd.

Yuji Kurotsuchi

Hiromitsu Kimura

Kyoji Marumoto

A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M≥2, L≥M+1, and M+N≥L+1.

Synchronous reset signal generation circuit and digital processing device

A semiconductor device of the present invention is provided with a terminal for connecting a plurality of buses to the outside of the semiconductor device, a bus interface circuit for treating the plurality of buses as the same bus within the semiconductor device and a controller connected to the bus interface circuit.

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Kyoto, Japan

Yuji Kurotsuchi