Shinko Electric Industries Co., Ltd.

Yuji Kunimoto

Hideaki Sakaguchi

Takaharu Yamano

Tsuyoshi Kobayashi

Tadashi Arai

Koichi Tanaka

Hajime Iizuka

Toshio Kobayashi

Kiyoaki Iida

Tetsuya Koyama

Tomoaki Mashima

Takashi Yanagisawa

Naoyuki Koizumi

Akihiko Tateiwa

Noriyoshi Shimizu

Jun Furuichi

Masahiro Kyozuka

Kenta Uchiyama

Atsunori Kajiki

A wiring board includes an insulator layer, a wiring layer including a wiring pattern and formed on one surface of the insulator layer, an inorganic layer covering a region of the one surface of the insulator layer not formed with the wiring layer, and covering an upper surface and side surfaces of the wiring pattern along a concavo-convex of the wiring pattern, and a shield part covering the wiring pattern via the inorganic layer.

Wiring board

An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Electronic part embedded substrate and method of producing an electronic part embedded substrate

A wiring board includes: a core substrate including: a metal plate having first through holes; a first insulating layer covering an upper surface and a lower surface of the metal plate and inner wall surfaces of the first through holes; through electrodes penetrating the first insulating layer in a thickness direction and each having an upper end surface; a first wiring layer formed on a lower surface of the first insulating layer and connected to the through electrodes; a wiring structure formed on an upper surface of the first insulating layer; and an outermost insulating layer formed on a lower surface of the core substrate. A wiring density of the wiring structure is higher than that of the core substrate. The metal plate is located at a side of the wiring structure with respect to a center of the first insulating layer in a thickness direction thereof.

Wiring board, and semiconductor device

A wiring substrate includes an insulating layer, a stack including wiring layers and photosensitive-resin insulating layers on a first surface of the insulating layer, a wiring layer on a second surface of the insulating layer, having a lower wiring density than the wiring layers, a metal core plate buried in the insulating layer and positioned on the stack side with respect to the center of the insulating layer in its thickness direction, and a via wiring buried in the insulating layer to have a first end face exposed at the first surface and joined to the lowermost one of the wiring layers, and a second end face joined to the metal core plate. The first surface and the first end face are substantially flush with each other. The wiring layers include a signal line, and a ground line concentrically formed around the signal line, with a predetermined interval therebetween.

Wiring substrate

A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring interval wider than the first wiring interval, a metal plane layer formed on a portion of a first insulation layer formed on the first wiring layer, the first wiring part being located below the portion, a second insulation layer formed on the first insulation layer and the metal plane layer and having a first via hole and a second via hole, a second wiring layer formed on the second insulation layer and connected to the first wiring layer via a first via conductor formed in the first via hole, and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via a second via conductor formed in the second via hole.

Wiring substrate and method of manufacturing the same

Chip embedded substrate and method of producing the same

A wiring board includes first and second insulating layers, first and second through holes, a via, a plane layer, and signal wirings. The first insulating layer covers a first wiring layer. The first through hole opens on a surface of the first insulating layer and exposes a surface of the first wiring layer. The via fills the first through hole. The plane layer is connected to the via and is stacked on the first insulating layer. The second through hole opens on a surface of the plane layer and exposes the surface of the first insulating layer. The second insulating layer at least partially fills the second through hole and covers the plane layer. The signal wirings are stacked on the second insulating layer. The first through hole overlaps the signal wirings in a plan view. The second through hole does not overlap the signal wirings in a plan view.

Wiring board, semiconductor device, and method for manufacturing wiring board

A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.

Wiring substrate, method of manufacturing the same, and semiconductor device

A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Semiconductor package and manufacturing method

A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device.

Semiconductor device

At least one electronic component having a plurality of terminals on one of surfaces is temporarily fixed to a surface of a first support with a first adhesive layer in such a manner that the terminal side of the electronic component faces the first support. A second support having a second adhesive layer is fixed to the electronic component in order to interpose the electronic component between the first support and the second support. The first support and the first adhesive layer are peeled. The electronic component on the second support is sealed with a sealing resin in such a manner that at least a part of the terminals of the electronic component is exposed. An insulating resin layer and a wiring layer to be electrically connected to the terminal of the electronic component are stacked on the electronic component and the sealing resin.

Growing community of inventors

Nagano, Japan

Yuji Kunimoto