Fujitsu Corporation

Nec Lcd Technologies, Ltd.

Nlt Technologies, Ltd.

Sony Corporation

Yuji Kondo

Yuichiro Ajima

Shinya Hiramoto

Michiaki Sakamoto

Nobuaki Honbo

Kazuya Yoshimoto

Ken Sumiyoshi

Hidenori Ikeno

Koji Mimura

Sounosuke Takahashi

Takashi Arakawa

Naozumi Aoki

Masatake Baba

An arithmetic processor performs arithmetic processing, and a synchronization processor, including first registers, performs synchronization processing that includes a plurality of processing stages to be processed stepwise. The arithmetic processor sends, to the synchronization processor, setting information to be used in a predetermined processing stage of the synchronization processing, and instruct the synchronization processor to execute the predetermined processing stage for the arithmetic processing. Each of the first registers includes a setting information management area to manage the setting information received from the arithmetic processor, and a destination status area to store a usage state of each of destination registers which are used in a next processing stage following the predetermined processing stage. The synchronization processor executes the predetermined processing stage by transferring data between the first registers to cause the synchronization processing to proceed to the next processing stage.

High-speed barrier synchronization processing that includes a plurality of different processing stages to be processed stepwise with a plurality of registers

A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.

Arithmetic processing device and memory access method

A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (&#x3e;M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.

Memory access controller with refresher and scrubbing mechanism and memory access control method thereof

An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.

Arithmetic processor and arithmetic apparatus

A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Processor and information processing apparatus

An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Processor and information processing apparatus for checking interconnects among a plurality of processors

In a parallel computer system having multiple information processing apparatuses, a first information processing apparatus includes circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited calculation target data; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses. This configuration makes it possible to achieve highly-precise collective average calculation without requiring bit expansion.

Information processing apparatus, parallel computer system, and method for control

An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.

Information processing apparatus, information processing system and method of controlling information processing system

A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

Computation node device, parallel computer system, and control method for computation node device

To provide a liquid crystal display device capable of switching the range of viewing angles while being able to reduce the cost and thickness of the device, and to provide an electronic appliance having the same. The display device according to the present invention includes: a liquid crystal type display panel having a diffusive reflection part which diffusively reflects light irradiated from the front side while transmitting light from the back side; and a backlight source disposed on a back face of the display panel along the display panel for switchably outputting transmission light of different directivities.

Display device and electronic appliance

A projector apparatus for projecting an image to a projected surface by illuminating an image forming element using light from a light source is provided. The projector apparatus includes an apparatus casing containing the light source and the image forming element, and an air filter receiving portion provided in the apparatus casing and having an air intake through which air is drawn. The projector apparatus also includes a plurality of air filters having substantially the same size as an air intake opening area, a cooling fan causing air to flow into the projector apparatus through the air intake and causing the air to pass through the plurality of air filters, a first air channel directing a portion of the air to a front air filter, and a second air channel directing the remaining portion of the air to a rear air filter.

Projector apparatus

An active-matrix bistable display panel is provided in which a pixel electrode is formed at each intersection of each of a plurality of scanning lines in a row direction and each of a plurality of signal lines in a column direction and a display state is made to occur depending on a voltage of each of the pixel electrodes, a signal-line driving unit is provided in which the plurality of signal lines is connected to a plurality of terminals and image inputs are sequentially divided into a plurality of image inputs and a plurality of image signals are supplied sequentially to the plurality of terminals in a time-division manner, and a scanning-line driving unit is provided in which each scanning line making up the plurality of groups is sequentially driven for each of the groups, wherein each of TFTs (Thin Film Transistors) is made active so as to supply an image voltage to each of pixel electrodes.

Active-matrix bistable display device

A LCD unit () has a first and a second LCD panels () which are stacked one on another. The first LCD panel () includes a color filter layer (), and is configured as a color LCD panel for performing a color display. The second LCD panel () is configured as a monochrome LCD panel for performing a monochrome display based on an image source. The first LCD panel () displays an image, which is obtained by averaging the image data of the image source by using an arithmetic unit, which averages the image data pixels disposed within a range specific distance apart from a central pixel.

Stacked multi-panel LCD device comprising a first driving signal for driving at least one of said stacked LCD panels and a second driving signal for driving another of said stacked LCD panels being obtained by applying an averaging processing to said first driving signal

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Kawasaki, Japan

Yuji Kondo