Sanyo Electric Co., Ltd.

Yuji Kitamura

Minoru Hamada

Yasuki Rai

Nobuhiro Mitani

Ichiro Nakatsukasa

A gate array arrangement formed on a semiconductor chip includes a plurality of I/O cells aligned along the four sides of the chip and a plurality of basic cells aligned in a plurality of rows extending parallelly to each other. A ground bus line and a power bus line extend in a space between the I/O cells and basic cells. The lines from the I/O cells are connected to the bus lines, and lines from basic cells are connected to bus lines. In this manner, the power supply lines between the I/O cells and basic cells are connected indirectly through the bus line, thereby allowing the determination of pitch of the I/O cells and pitch of basic cells independently of each other.

Gate array arrangement

An insulating film O is formed on a semiconductor substrate S. On the insulating film O, first electrodes M.sub.1 are disposed in parallel and second electrodes M.sub.2 are also disposed in parallel. The first electrodes M.sub.1 are insulated from the second electrodes M.sub.2 and the first electrodes M.sub.1 and the second electrodes M.sub.2 are disposed such that one side of a first electrode M.sub.1 and one side of a second electrode M.sub.2 are adjacent to each other. On the surface regions of the semiconductor substrate S between the respective other sides of the first electrodes M.sub.1 and the second electrodes M.sub.2, high concentration regions S.sub.3 are formed using the first and second electrodes M.sub.1 and M.sub.2 as a mask without causing deviation in positioning. To the first electrodes M.sub.1 and the second electrodes M.sub.2, a first clock pulse .phi..sub.1 and a second clock pulse .phi..sub.2 are applied respectively and electric charges are transferred in response to these clock pulses.

Charge coupled device for transferring electric charge

An analog value storing apparatus comprises a semiconductor field-effect device, including a substrate, a source and drain formed to define a channel region, a floating gate embedded in an insulating layer on the channel region, a control gate connected to the ground on the insulating layer above the floating gate, a write voltage source coupled to the source to supply a write voltage to charge the floating gate, a resistor having a relatively high resistance value inserted between the write voltage source and the source, and an analog value voltage source connected to the drain. As a result, the floating gate begins to be charged with the write voltage and the analog voltage and stops being charged with the voltage at the source determined as voltage division of the write voltage and the analog voltage by the high resistance value of the resistor and the internal resistance value of the device. Preferably, an array of a plurality of such devices is used and an analog signal is stored in the form of a series of sampled analog values sampled from the analog signal at the timing of addressing while such devices are addressed sequentially. The stored analog values are read out while the devices are addressed, whereby and original analog signal is reproduced.

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Gifu, Japan

Yuji Kitamura