Texas Instruments Corporation

Yuji Iwasawa

Takayuki Niuya

A latch-type SRAM memory cell having a number of MOS transistors arranged to maintain symmetry with each other circuitwise, in which the source regions of the MOS transistors are arranged so as to be adjacent semiconductor regions of opposite conductivity with respect thereto. Zener diodes are formed between the adjacent source and semiconductor regions with each of these Zener diodes being connected between their respective source regions and a power supply. Since current to each source region of paired MOS transistors flows effectively to the power supply or ground side via a Zener diode using a tunneling effect, a rise in the source region potential can be reduced, and an increase in the transistor threshold value can be controlled. In this way, symmetry of the paired transistors can be maintained, and the performance of the memory cell, e.g., memory cell data retention ability and drive current ability, can be increased. In addition, a high degree of integration and miniaturization of the device can be achieved with the Zener diodes, and a large degree of tolerance can be obtained for fluctuations in silicification conditions and fluctuations in surface concentration of the source and drain regions, as well as for variations during contact formation. Because of this, it will be possible to produce good quality, highly integrated semiconductor devices at high yields.

Growing community of inventors

Tsukuba, Japan

Yuji Iwasawa