Sony Corporation

Sony Semiconductor Solutions Corporation

Yuji Gendai

Yoshihiro Komatsu

Nobuyoshi Kobayashi

Junji Toyomura

Norifumi Kanagawa

Satoshi Kato

Masaaki Ishihara

Yasuaki Hisamatsu

Norio Shoji

Kenichi Takamiya

Kimimasa Senba

Nobuyuki Asai

Kazumasa Nishimoto

Tadafumi Nagata

The present disclosure relates to an image sensor, an electronic device, and a method for generating a tessellation tile that allows pattern noise that can be generated in an image output from an image sensor including column ADCs or area ADCs to be less visible. An image sensor according to a first aspect of the present disclosure includes analog digital converters (ADCs), each of the ADCs being provided for a column, wherein the ADCs associated with the respective columns are configured to read charge signals simultaneously from pixels arranged on lines different from one another of the respectively associated columns, the number of ADCs being a predetermined number corresponding to the number of columns, the columns being adjacent to one another. The present disclosure is applicable to any electronic device including an image sensor.

Image sensor and electronic device

An image sensor includes a capacitor, a low-impedance virtual battery, and a boost current source. The capacitor includes one end connected to a vertical signal line and the other end. The low-impedance virtual battery is connected to the other end of the capacitor and configured to detect a current flowing in the capacitor. The boost current source is configured to provide a boost current to the vertical signal line, the boost current being a current corresponding to the current flowing in the capacitor.

Image sensor, driving method, and electronic apparatus

A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

Solid-state imaging device, drive method thereof and camera system

There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of FETs (Field Effect Transistors), the gate line connecting gates of the FETs each being a load component in the current mirror.

Current mirror, control method, and image sensor

A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Signal processing circuit, solid-state imaging device, and camera system

Disclosed herein is a signal processing circuit including: a main path configured to transmit an input signal and output an actual signal; and a negative feedback path configured to feed back the actual signal to an input stage of the main path, wherein the main path includes a main path block that receives an input signal and outputs an actual signal, the negative feedback path includes a negative feedback block that generates a control signal and supplies the control signal to an input part of an input signal of the main path; a replica block that is supplied with a control signal of the negative feedback block to output a pseudo actual signal, and imitates the main path block; and a signal delay block that delays a pseudo actual signal of the replica block by a dead time of a loop.

Signal processing circuit, AGC circuit, and recording and playback device

An optical disk reproducing device includes: a signal reproducing section configured to read and decode information recorded on an optical disk by an optical pickup unit, and reproduce the information, wherein the signal reproducing section includes a gain controlled amplifier circuit configured to amplify an radio frequency signal generated from a light receiving element, an automatic gain control circuit configured to control a gain of the gain controlled amplifier circuit, and a signal processing section configured to derive a part of an automatic gain control value generated in the automatic gain control circuit, and generate a control signal for adjusting one of an optical system path and a detection system path for controlling the optical pickup unit.

Optical disk reproducing device and optical disk recording and reproducing device

A Phase Locked Loop circuit, includes: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of the main path; and a local feedback path through which feedback is carried out from a path middle of the main path to a path middle of an input stage side; the main path including a phase detector, a loop filter, and a controlled oscillator, and the local feedback path including a replica portion, a delay portion, a first subtracter, and a second subtracter.

Phase locked loop circuit

A signal apparatus is provided. The signal value holding apparatus including a determining section to determine a magnitude relationship between a signal value of an input signal and a signal value of a prescribed feedback signal, a first holding section to hold the signal value determined to be larger by the determining section, a subtracting section to subtract a prescribed value from the signal value held by the first holding section and output a result as the feedback signal, and a second holding section to receive the signal value held by the first holding section and hold the signal value supplied from the first holding section when the signal value of the input signal becomes smaller than the signal value of the feedback signal based on a determination result of the magnitude relationship between the signal values by the determining section.

Signal value holding apparatus, signal value holding method, signal value control system, signal value control method, playback apparatus, and playback method

Differential signals output by a transfer unit of a latch stage are fed back to a comparator stage as negative feedback signals through a feedback circuit including a differential amplifier comprising two transistors. In this configuration, amplitudes of signals supplied to the transfer unit are stabilized by a feedback effect provided by the feedback circuit to become independent of a through-rate of an input signal supplied to the comparator stage. To be more specific, if the through-rate is high, the amplitudes are reduced, but if the through-rate is low, the amplitudes are increased. As a result, variations in sampling delay related to sampling clock signals are suppressed. With this configuration, for example, harmonic distortions in a flash A/D converter are suppressed as well.

Comparator circuit

To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit. An asymmetry correcting circuit includes a first envelope detection circuit for detecting the envelope of a positive peak of an input signal waveform; a second envelope detection circuit for detecting the envelope of a negative peak of the input signal waveform; an adding circuit for producing a sum voltage of the positive peak voltage and the negative peak voltage; a smoothing circuit for smoothing the sum voltage; a multiplying circuit for multiplying the smoothed sum voltage by a predetermined offset adjustment coefficient; and a quantization reference voltage control circuit for DC-wise shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the ADC in conformity with the offset derived from the asymmetry of the input signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity.

Asymmetry correcting circuit and information reproducing apparatus using the same

The invention provides a logic circuit which has a sufficient load driving capacity even in its operation with a low power supply voltage and can operate at a high speed. In a next stage to a differential circuit having an output stage for which an emitter followers are used, a folding circuit in which a pair of transistors of a diode connection are used to raise the signal level of differential outputs of the differential circuit.

Logic circuit

An ADC having a sparkle suppression capability equivalent to that of a full bit Gray encoding method and preventing criss-crossing of interconnections nor an increase of the pipeline delay, wherein a resistor string for generating reference voltages to be compared with an analog input signal is folded 2 times or a multiple thereof corresponding to the number n of most significant bits of the output bit ADB of the related ADC. It has a first encoder for encoding the most significant n bits and outputting a Gray code, second encoders for encoding least significant bits and outputting the same, a first output circuit for converting the Gray code output from the first encoder to a binary code and generating most significant n bits, and a second output circuit for generating least significant bits by using the digital code generated by the first output circuit and the output of the second encoder.

Flash type analog-to-digital converter

A plurality of comparators are arranged in parallel, and novel constructions are employed for emitter followers or like circuits of input circuits of the comparators or for reference voltage supplying circuits for use for those circuits, thereby to improve the differential linear distortion or some other characteristic and reduce noise without the input capacitance. Further, an ECL circuit for use for signal processing is provided with a power saving function to reduce the power dissipation.

Growing community of inventors

Kanagawa, Japan

Yuji Gendai