Texas Instruments Corporation

Yujendra Mitikiri

Minkle Eldho Paul

Anukruti Chakraborty

Seetharaman Janakiraman

Vikram Varma

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Kickback compensation for a capacitively driven comparator

An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.

High speed high resolution ADC using successive approximation technique

An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.

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Hyderabad Telangana, India

Yujendra Mitikiri