Fujitsu Corporation

Yuichirou Chikamatsu

Hideo Abe

Yasuo Tezuka

Yoshio Tamura

Packet buffer equipment in which a buffer and time for packet assembly is utilized for packet header analysis and addition processing to obtain increased efficiency. The equipment aims to receive virtual channel (VC)-multiplexed ATM cells to assemble into a packet on a VC basis maintaining each received cell, to output on a packet basis. As an embodiment, cells are assembled into a packet by storing cells from the top cell to the end cell into a packet buffer memory consisting of a plurality of cell buffers to store cells. Also, a sequence controller is provided for detecting the write completion of a new header cell, and for connecting a packet in packet-under-assembly queue constituted by under-assembly pointer into an output-wait queue.

Packet buffer equipment

This invention relates to an IP processor, and more particularly, provides an IP processor that reduces network load when a plurality of IP processors connected to ATM switches are used in edge portion of an IP network. The IP processor is comprised of a line interface unit for interfacing with an ATM switch, an IP packet buffer unit for temporarily storing an IP packet from the line interface unit, and sending out the IP packet after address resolution to the line interface unit, and an IP address resolution unit that responds to address resolution request from the IP packet buffer unit and returns the destination address information after address resolution, wherein the IP packet buffer unit sends out, when destination address information cannot be retrieved from the IP address resolution unit, the temporarily stored IP packet to a transfer route for direct transfer between IP processors.

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Kawasaki, Japan

Yuichirou Chikamatsu