Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuichiro Yamashita

Tzu-Jui Wang

Dun-Nian Yaung

Ching-Chun Wang

Jhy-Jyi Sze

Chen-Jong Wang

Chun-Yuan Chen

Shyh-Fann Ting

Hirofumi Sumi

Hsiao-Hui Tseng

Chun-Hao Chuang

Yen-Ting Chiang

Wei-Cheng Hsu

Chin-Chia Kuo

Kuo-Chin Huang

Ming-Chieh Hsu

Yu-Jen Wang

Hua-Mao Chen

Image sensor structures are provided. In some embodiments, an image sensor structure is provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate and extending from the top surface to the bottom surface of the substrate. The image sensor structure further includes a first isolation structure extending from the top surface of the substrate to a middle portion of the substrate and a second isolation structure formed extending from the bottom surface of the substrate to the middle portion of the substrate and in contact with the first isolation structure. The image sensor structure further includes a gate structure overlapping the light-sensing region, the first isolation structure, and the second isolation structure and a cap layer overlapping the gate structure, the light-sensing region, the first isolation structure, and the second isolation structure in a top view.

Image sensor

The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Backside diode design

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Extra doped region for back-side deep trench isolation

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Image sensor having a gate dielectric structure for improved device scaling

The present disclosure relates to an image sensor including a pixel along a substrate. The pixel includes a first semiconductor region having a first doping type. A second semiconductor region is directly over the first semiconductor region. The second semiconductor region has a second doping type opposite the first doping type and meets the first semiconductor region at a p-n junction. A ring-shaped third semiconductor region laterally surrounds the first and second semiconductor regions. The ring-shaped third semiconductor region has the first doping type. A ring-shaped fourth semiconductor region laterally surrounds the ring-shaped third semiconductor region. The ring-shaped fourth semiconductor region has the second doping type. A ring-shaped fifth semiconductor region is directly over the ring-shaped third semiconductor region and has the second doping type.

Image sensor with photosensitivity enhancement region

Growing community of inventors

Hsinchu, Taiwan

Yuichiro Yamashita