Samsung Electronics Co., Ltd.

Yuichiro Sasaki

Sangjin Hyun

Weonhong Kim

Seungha Oh

Yongho Ha

Sungkeun Lim

Taehyeon Kim

Pil-Kyu Kang

Kyungin Choi

Taegon Kim

Jaeyoung Park

Kughwan Kim

Hongshik Shin

Tae Gon Kim

Bong Soo Kim

Seung Hyun Song

Kyung In Choi

Pilkyu Kang

Abraham Yoo

Alexander Schmidt

Yoshiya Moriyama

Heung Soon Lee

Sang Woo Lee

Tae-Gon Kim

Hong-Shik Shin

A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

Three-dimensional semiconductor devices

An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

Method of manufacturing an integrated circuit device

A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Semiconductor device

A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

Method of fabricating semiconductor device

Integrated circuit device and method of manufacturing the same

A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).

Semiconductor devices

A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Method of forming a semiconductor device having impurity region

Semiconductor device having impurity region

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Seoul, South Korea

Yuichiro Sasaki