Renesas Electronics Corporation

Yuichiro Nariyoshi

Daisuke Suzuki

Takashi Endo

Minoru Saeki

Seiji Kobayashi

Yoshiyuki Amanuma

Yosuke Tanno

A semiconductor device includes a CPU, an EEPROM, and a ROM. The ROM includes an encryption area and a non-encryption area and the encrypted firmware is stored in the encryption area. The semiconductor device includes a decrypter which holds the encryption key, decrypts the encrypted firmware, and supplies the decrypted firmware to the CPU. The EEPROM includes a system area to which an access from the CPU is forbidden in a user mode. The encryption key is divided into split keys of plural bit strings, and stored in the distributed address areas in the system area. An encryption key reading program which is not encrypted is stored in the non-encryption area of the ROM. Executing the encryption key reading program, the CPU reads and reconfigures plural split keys stored in the EEPROM in a distributed manner to restore the encryption key and supplies the restored encryption key to the decrypter.

Semiconductor device and encryption key writing method

There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.

Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies

The present invention is directed to improve leak analysis resistance by improving randomness of a pseudorandom number. A pseudorandom number generator as a representative embodiment of the invention includes a shift resistor obtained by coupling a plurality of flip flop circuits and can generate a pseudorandom number by shifting signals by the shift register synchronously with a clock signal. A shift amount changing circuit capable of changing a shift amount in the shift register in accordance with a control signal supplied from the outside of the pseudorandom number generator is provided. By changing the shift amount in the shift register in accordance with a control signal supplied from the outside of the pseudorandom number generator by the shift amount changing circuit, it becomes difficult to make outputs of the pseudorandom number generator the same. By using such a pseudorandom number generator, leak analysis resistance can be improved.

Growing community of inventors

Tokyo, Japan

Yuichiro Nariyoshi