Kabushiki Kaisha Toshiba

Yuichiro Mitani

Daisuke Matsushita

Takao Marukame

Yasushi Nakasaki

Koichi Kato

Yusuke Higashi

Jiezhi Chen

Tatsuo Shimizu

Ichiro Mizushima

Hirotaka Nishino

Shigeru Kambayashi

Izumi Hirano

Shosuke Fujii

Tetsufumi Tanamoto

Yoshifumi Nishi

Masamichi Suzuki

Masahiro Koike

Koichi Muraoka

Hideki Satake

Masayasu Miyata

Masahiro Kashiwagi

Yoshio Ozawa

Masayuki Tanaka

Mitsuhiro Noguchi

Yoshitaka Tsunashima

Naoki Yasuda

Shinichi Yasuda

Kiwamu Sakuma

Yuki Sasaki

Kiyotaka Miyano

Yukie Nishikawa

Akira Goda

Kazuya Matsuzawa

Takahiro Kurita

Shigehiko Saida

Yoshihiko Moriyama

Shigeto Fukatsu

Haruki Toda

Tatsuya Kishi

Hiroyuki Nagashima

Shinobu Fujita

Ryosuke Iijima

Hiroki Noguchi

Akira Nishiyama

Kenichi Murooka

Atsushi Shimbo

Akira Takashima

Nobutoshi Aoki

Jun Deguchi

Satoru Takase

Iwao Kunishima

Toshihide Ito

Koichiro Zaitsu

Teruyuki Ohashi

Kazunori Kanebako

Katsuki Matsudera

Fumihiko Tachibana

Akira Toriumi

Mitsuhiro Tomita

Misako Morota

Shuichi Toriyama

Kouichi Muraoka

Makoto Morimoto

Riichiro Takaishi

Haiyang Peng

Akiko Nara

Kuniharu Takahashi

Akiko Masada

A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.

Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.

Memcapacitor, neuro device, and neural network device

A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.

According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

Memory system, error correction device, and error correction method

According to an embodiment, a decoding device includes a variable node processor, a check node processor, a first forwarder, and a second forwarder. The variable node processor is configured to perform variable node processing on variable nodes defined by a code and output first messages. The check node processor is configured to perform check node processing on check nodes defined by the code based on the first messages and output second messages. The first forwarder is configured to forward one or more first messages remaining after excluding messages to be forwarded to one or more check nodes corresponding to one or more of the second messages having been stored in ae storage, to the check nodes. The second forwarder is configured to forward the second messages to the variable nodes and forward the one or more of the second messages to the storage.

Decoding device and decoding method

According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.

Imaging element for use with a retina chip, imaging apparatus including the same, and semiconductor apparatus included in the same

According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.

Authentication system, authentication device, and authentication method

According to an embodiment, an information processing system includes a time constant processor and a pattern generator. The time constant processor binarizes values indicating a plurality of unit circuits each including a gate insulating film on the basis of a time to emission indicating a time from when a defect in the gate insulating film captures a carrier in a channel current caused to flow by application of a gate voltage to the unit circuits to when the defect emits the carrier. The pattern generator generates a pattern unique to the unit circuits using the values indicating the respective unit circuits binarized by the time constant processor.

Information processing system and semiconductor device

A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0&#xb0; to 10&#xb0; with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80&#xb0; to 90&#xb0; with respect to a &#x3c;000-1&#x3e; direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1&#xd7;10cmor more and a maximum concentration of hydrogen (H) in the region being 1&#xd7;10cmor less.

Semiconductor device and method for manufacturing the same

According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.

Decoding device, decoding method, and memory system

According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.

Semiconductor device and reading method

This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.

Semiconductor device with polycrystalline silicon film

According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.

Authentication device, authentication method, and computer program product

A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage.

Memory system, control system and method of predicting lifetime

A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.

Nonvolatile semiconductor memory

Growing community of inventors

Kanagawa-ken, Japan

Yuichiro Mitani