Mitsubishi Denki Kabushiki Kaisha

Hitachi-kokusai Electric Inc.

Renesas Technology Corp.

Yuichiro Komiya

Tsukasa Ooishi

Muneaki Yamaguchi

Hideto Hidaka

Mikio Asakura

Haruhiro Koto

Wataru Ito

Kiyohiro Furutani

Takashi Kono

Katsuyoshi Mitsui

Takeshi Kajimoto

Hideharu Hattori

Kei Hamade

Yuto Ikeda

Kazunari Iwanaga

Shinya Ogura

Jun Nakai

Junichi Togashi

Yohei Akimoto

Atsushi Sassa

Yoshiki Agata

Masaya Okada

Hiroaki Nakakita

Kunihiro Soga

Disclosed is an autonomous distributed system for detecting and tracking a falling object within a region being monitored by using a plurality of camera assemblies cooperating with each other, and disclosed is a camera assembly therefor. Each of the camera assembly, normally, operates in a falling object detecting mode, but, when detecting a falling object, shifts to a tracking mode. In the tracking mode, a degree of danger of the falling object is determined by referring to the size of the falling object in real space and the movement of a falling. In addition, when the falling object is further tracked and moved outside of the angle of view, a search request including information of the degree of danger as to the falling object is issued to surrounding camera assemblies, such that the multiple camera assemblies search for the falling object in cooperation.

System for tracking object, and camera assembly therefor

The purpose of the present invention is to provide a technology which adaptively switches video analysis methods according to a congestion situation within a video, and which carries out a suitable video analysis by a limited computational volume. Provided is an image processing device, wherein a congestion estimation unitestimates a congestion situation within a video which is acquired from an image input unit. A control unitswitches methods for video analysis according to the congestion situation. In a situation of low congestion, an image analysis unit for use in normal situationscarries out the video analysis by a basic method. In a situation of high congestion, an image analysis unit for use in congested situationscarries out a high-precision video analysis, such as an analysis which spans a plurality of frames.

Image processing device

A similar image search system is provided and searches for images similar to a search key image, where a number of searched images of person are classified into a number of groups based on a similarity between the respective images. A grouping display is performed in which at least one of the images that belongs to each group is displayed in a display region that is provided for each group. The grouping display is performed in such a manner that the order of the similarity between each group and the search key image can be visually recognized.

Similar image search system

The purpose of the present invention is to provide image processing technology that can reduce shimmering in the entirety of images that include both still regions and moving bodies. This image processing device finds gradient distribution for each of a frame to be corrected and a frame for correction, changes, according to the degree of similarity in the gradient distribution, the proportion in which the frame to be corrected and the frame for correction are used, and then corrects the frame to be corrected using the frame for correction (see FIG.).

Image processing device, imaging device, monitoring system, encoding device, image processing method

An image processing apparatus for reducing fluctuations due to a heat haze in an image including a stationary region and a moving object obtains histogram of gradation distribution for each of a target image to be corrected and a frame for correction, and corrects the target image by using the frame for correction while changing a mixing ratio between the target image and the frame for correction depending on similarity between histograms. To adaptively control a size of image blocks for the histograms, the apparatus calculates two indices having different robustness to deformation of an object from image blocks of each of the target image and the frame for correction, and determines suitability of the image block size based on a relationship of the indices. The difference between the histograms and the sum of absolute differences (SAD) between the pixel values can be used as the two indices.

Image processing apparatus and image processing method

Disclosed is a method for correcting for shimmer due to thermal turbulence, even for moving subjects, on a time smoothed base. The device is provided with: a movement compensation means that, for a correction-targeted block of a correction-targeted image within an input image, uses a temporally proximate correction image to derive movement information about a moving object, performs motion compensation, and outputs a correction block and a cost value; and a shimmer correction means that carries out time averaging processing, in accordance with the cost value, of the correction-targeted block and the correction block, and outputs a corrected block in which shimmer of the moving object has been corrected, and correction information. Through two-stage motion detection, the movement compensation means extracts and compensates for movement of a moving object, in a manner unaffected by thermal turbulence.

The boosting circuit provided in a semiconductor device includes a ring oscillator generating a pump clock having constant periods, a pump capacitor for performing a boost operation, and a pump capacitor input control unit provided between one electrode of the pump capacitor and the ring oscillator. The pump capacitor input control unit fixes one electrode of the pump capacitor to a prescribed voltage to apply stress of a desired level to the pump capacitor in response to a control signal that is activated at the time of burn-in test.

Semiconductor device including power supply circuit conducting charge pumping operation

A potential detecting circuit is provided for detecting prescribed potential and determining whether the detected prescribed potential has reached a prescribed level. The circuit includes an output node; a reference current supply for supplying a prescribed reference current to the output node; a detection node for receiving the prescribed potential; a comparing current supply circuit responsive to the prescribed potential applied to the detection node for supplying a comparing current to the output node; and a transistor having a control electrode receiving a reference potential which is independent of a power supply voltage and is at a level different from a power supply potential. The transistor has one conduction electrode connected to the detection node and the other conduction electrode connected to the comparing current supply circuit. Current change in the transistor, corresponding to a change in the prescribed potential applied to the detection node, changes the comparing current. Accordingly, current consumption may be reduced, and a stable detection level may be maintained, which is not dependent on fluctuations in temperature or fluctuations in a power supply potential applied to the circuit.

Potential detecting circuit for determining whether a detected potential has reached a prescribed level

A semiconductor memory device has a half Vdds generating circuit. The half Vdds generating circuit includes reference voltage generating circuits, a selecting circuit, and a driver circuit. In a normal mode, the driver circuit receives voltages Vnd1 and Vpd1 obtained by dividing an array operation voltage Vdds from the reference voltage generating circuit and outputs a precharge voltage Vb1 from an output node. In a test mode, the driver circuit receives voltages Vnd2 and Vpd2 obtained by dividing the voltage Vddp from the reference-voltage generating circuit, and outputs a precharge voltage Vb1 from the output node. As a result, a voltage as a reference used to generate an intermediate voltage can be switched between the normal mode and the test mode.

Semiconductor memory device capable of switching reference voltage for generating intermediate voltage

Reference potential generating circuit includes an output N channel MOS transistor connected between a power supply node and an output node; an output P channel MOS transistor connected between output node and ground node; a control P channel MOS transistor having its source connected to a power supply node and its gate connected to the output node; a control N channel MOS transistor having its source connected to the ground node and its gate connected to the output node; a diode connected reference N channel MOS transistor connected in series with the control P channel MOS transistor; and a diode connected reference P channel MOS transistor connected in series between the control N channel MOS transistor and the reference N channel MOS transistor.

Reference potential generating circuit

The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

Method for making level converting circuit, internal potential generating circuit and internal potential generating unit

Level converting circuit for converting level of an input signal,

A potential detecting circuit includes an output node, a reference current supplying circuit for supplying a prescribed reference current to the output node, a detection node to which the potential to be detected is applied, and a comparing current supplying circuit, responsive to the potential applied to the detection node, for supplying a comparing current to the output node. The comparing current supplying circuit includes a detection resistance element through which a detection current flows in response to the potential applied to the detection node, and a current mirror circuit responsive to the detection current for controlling supplying the comparing current. When the potential applied to the detection node attains the prescribed detection level, an additional current supplying circuit supplies an addition current to the output node in addition to the comparing current.

Potential detecting circuit for determining whether a detected potential

A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.

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Hyogo, Japan

Yuichiro Komiya