Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Seiko Intruments Inc.

Yuichiro Kitajima

Jun Osanai

Kazutoshi Ishii

Yukimasa Minami

Miwa Wake

Keisuke Uemura

Tomomitsu Risaki

Naoto Saitoh

Hideo Yoshino

Naoto Kobayashi

Provided is a semiconductor device including a fuse element arranged on an interlayer insulating film formed on a semiconductor substrate. The fuse element is formed of polysilicon and a silicide region arranged on an upper surface of the polysilicon. A region of the polysilicon included in a range to be irradiated with a laser beam in plan view is non-doped polysilicon into which impurities are not introduced. With this structure, it is possible to provide the semiconductor device including the fuse element, which can be stably cut with a laser beam while an underlying film is not damaged.

Semiconductor device including a fuse element

Provided is a semiconductor device in which a fuse element, which is cuttable by a laser, can be stably cut. The fuse element includes an upper fuse element, a lower fuse wiring line, and a fuse connecting contact such that, in cutting the fuse element by a laser, the lower fuse wiring line is protected by an inter-layer film, and only the upper fuse element is efficiently melted and evaporated. In addition, the contact for connecting the upper fuse element and the lower fuse wiring line to each other is formed at a center of a laser irradiation region, and hence the connection portion receives the energy of the laser most efficiently.

Semiconductor device

A semiconductor device has first and second NMOS transistors and an internal circuit, all formed in the same semiconductor substrate. The first NMOS transistor has a gate connected to a power supply terminal configured for connection to a power supply, a source and a back gate connected to an internal ground node, and a drain connected to a ground terminal configured for connection to the power supply. The second NMOS transistor has a gate connected to the ground terminal, a source and a back gate connected to the internal ground node, and a drain connected to the power supply terminal. The internal circuit is configured to operate with a voltage between the power supply terminal and the internal ground node. During a normal connection state in which the power supply is normally connected to the semiconductor device, current flows through the internal circuit and the second NMOS transistor.

A semiconductor device includes a fuse element that can be cut and removed by laser irradiation. The fuse element has a large width portion having a large sectional area to be irradiated with a laser spot, and two small width portions having a small sectional area connected to opposite sides of the large width portion. Penetration of moisture is suppressed even after cutting of the fuse element since the large width portion is removed by the laser irradiation and only the small width portions having the small sectional area remain as exposed cut surfaces.

Provided are a battery protection IC and a battery device, which are capable of ensuring safety even when a charger is connected in a reverse direction. The battery protection IC includes a first switch element provided between an overcurrent detection terminal and a VDD terminal so that, when the charger is connected with reverse polarity, the first switch element interrupts a current path between the overcurrent detection terminal and the VDD terminal. The battery protection IC further includes a second switch element provided between a charge control terminal and the VDD terminal so that, when the charger is connected with reverse polarity, the second switch element interrupts a current path between the charge control terminal and the VDD terminal.

Battery protection IC and battery device

By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.

Semiconductor device having a thick gate insulating film covering bird's beak region

A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.

Semiconductor device having resistor formed of a polycrystalline silicon film

A semiconductor device has a semiconductor chip, an internal circuit region arranged on an inner side of the semiconductor chip, and a bonding pad region arranged adjacently to the internal circuit region. A diode-type ESD protection circuit is formed of a junction between a first conductivity type diffusion layer for fixing a substrate potential of the semiconductor chip and a pair of second conductivity type diffusion layers arranged on an inner side of the first conductivity type diffusion layer. The first conductivity type diffusion layer is arranged on an entire peripheral region or a part of the peripheral region of the semiconductor chip with the peripheral region being outside of the internal circuit region and the bonding pad region. One of the pair of second conductivity type diffusion layers comprising a diffusion layer for breakdown adjustment at a junction portion with the first conductivity type diffusion layer.

Semiconductor device with a diode-type ESD protection circuit

An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again.

Method for manufacturing a semiconductor device having high-voltage and low-voltage transistors

Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.

Semiconductor device and manufacturing method thereof

A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.

Semiconductor device with resistor and fuse and method of manufacturing the same

Provided is an ESD protection element, in which: LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to easily satisfy a function required for the ESD protection element, the function of being constantly in an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again.

In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

Semiconductor device and method of manufacturing the same

In a method of manufacturing a semiconductor device, a first oxide film is formed in a convex shape on a field insulating film, a polycrystalline silicon film is formed on the first oxide film, and impurities are introduced into the polycrystalline silicon film. The polycrystalline silicon film into which the impurity is introduced is patterned so that a portion above the convex-shaped first oxide film becomes a resistance region of the resistor. A second oxide film is then formed on the patterned polycrystalline silicon film followed by the formation of a third oxide film on the second oxide film. The third oxide film and parts of the second oxide film and the polycrystalline silicon film are then removed to form a planarized surface including surface portions of the second oxide film and the polycrystalline silicon film.

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Chiba, Japan

Yuichiro Kitajima