Micron Technology Incorporated

Yuichi Yokoyama

Si-Woo Lee

A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

Array of capacitors and method used in forming an array of capacitors

Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

Widened conductive line structures and staircase structures for semiconductor devices

Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.

Capacitive units and methods of forming capacitive units

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

Bottom electrode contact for a vertical three-dimensional memory

Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers. A third vertical opening is formed through the vertical stack extending to expose second sidewalls adjacent areas where horizontal access devices will be formed. The sacrificial material is selectively etched to form first horizontal openings, removing the sacrificial material a first horizontal distance (D1) back from the third vertical opening. A fourth vertical opening is formed through the vertical stack to expose third sidewalls adjacent areas where storage nodes will be formed. The support-pillar material of the formed structural support pillars may serve as an etch stop in selectively etching to form the second horizontal openings.

Support pillars for vertical three-dimensional (3D) memory

Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).

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Boise, ID, United States of America

Yuichi Yokoyama