Renesas Electronics Corporation

Yuichi Takitsune

Kazunori Masaki

Motoshige Ikeda

Shinichi Suzuki

Techniques for detecting a loss of a received frame are provided. The communication apparatusincludes a receiving unitfor receiving a frame including a plurality of data, a first memoryfor temporarily storing a plurality of data, a second memoryfor storing a transfer rule of each data, a plurality of third memoriesto which each data is allocated, a processorassociated with each third memory, and a memory control unitfor controlling transfer of each data. The memory control unitoutputs an error when the first data is not the last data of the frame or the size of the first data is larger than the size defined by the second data in the case where the second data includes the last data flag.

Communication device

A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

Semiconductor device, electronic device module and network system

A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication interface. The peripheral module controls an external apparatus based on a specified control parameter. The communication interface includes a time register that is synchronized with the other apparatuses in time series. The communication interface issues a CPU interrupt and a peripheral module interrupt to the CPU and the peripheral module, respectively, if a successively settled correction time matches the time register. In response to the peripheral module interrupt, the peripheral module changes the control parameter from a current value to an update value. In response to the CPU interrupt, the CPU starts an update program to calculate the next update value for the control parameter and writes the calculated value to the peripheral module.

Microcomputer

A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

Growing community of inventors

Tokyo, Japan

Yuichi Takitsune