Mitsubishi Denki Kabushiki Kaisha

Yuichi Saito

Toyohiko Yoshida

Yukari Watanabe

Masahito Matsuo

Toru Shimizu

Kouichi Ishimi

Souichi Kobayashi

A data processor, with high processing performance in many fields of application, having a selector 41 which enables a cache memory of direct map system to be selectively used as a built-in cache memory or a built-in RAM in order to realize a data processor which can perform high-speed processing by decreasing the number of abortions of the processing as much as possible when branch is predicted in the pipeline processing mechanism, and an FB register 61B which holds an address to be accessed so that cache memory or external storage (main storage 28) may be accessed when branch is not predicted in the pipeline processing mechanism and only a cache memory may be accessed but accessing to the main storage 28 may be prohibited when branch is predicted, wherein the main storage 28 can be accessed by the address held in the FB register 61B at the moment it becomes accessible.

Data processor with cache memory

This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Multiple sequentially transferrable stackpointers in a data processor in

A microprocessor having a test mode wherein a test instruction including an instruction for executing the whole microprogram routine and a step-execution instruction for executing only one microinstruction of an arbitrary address in a micro ROM for easily diagnosing each internal function blocks by independently operating them, and a circuit for changing the content of sequence field of the microinstruction outputted to the microsequencer at executing the step-instruction. The circuit is used for executing the microprogram routine step by step with combining instructions which execute only one microinstruction, or a specified instruction between two continuous microinstructions of a microprogram routine, so that the cause of fault points in the microprocessor can be easily specified.

Microprocessor implementing single-step or sequential microcode

A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

Data processor with bus-sizing function

A microprocessor having a test mode wherein a test instruction including an instruction for executing a diagnosing microprogram routine which tests each function block inside of the microprocessor and an instruction which makes data scan in to various latches such as a latch at output portion of the micro ROM for easily diagnosing each internal function blocks by independently operating them, and the latch at the output portion of the micro ROM is allocated an address and is constituted to be loaded in and to store the data from outside of the microprocessor. A diagnosing instruction is loaded from the outside of the microprocessor and the microinstruction of an address allocated the latch is executed, thereby the cause of a fault in the microprocessor can be easily diagnosed.

Self-testing microprocessor with microinstruction substitution

A high-speed encoding apparatus retrieves the bit position of either one of the lowest order bit or the highest order bit having a first logical value. Such retrieving starts from a selected bit-position. The selected bit-position is defined by an input offset value Iofs4:Iofs0. The retrieved bit-position is the output of the encoder Oofs4:Oofs0. A zero detection circuit receives an n-bit data word, segments the n-bits into groups of predetermined length and for each group generates a zero detection when all bits in the group are zero. The zero detection circuit also masks the zero detections according to the high order bit states of the input offset value. A first encoder then generates the high order bits of the apparatus output offset in response to the masked and unmasked zero detections. A second encoder masks one or more of the groups according to the bit states of the input offset value, then generates encoded bit sets for each group. The high order bits of the output offset previously generated then are used to select which of the bit sets are used as the low order bits of the output offset.

Encoder apparatus

This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Growing community of inventors

Itami, Japan

Yuichi Saito