Fujitsu Corporation

Yuichi Ogawa

Terumasa Haneda

Toshiyuki Yoshida

Kazunori Masuyama

Yuuji Hanaoka

Hidenori Takahashi

Hiroshi Ishizawa

Tsukasa Makino

Hiroaki Ochi

Yuji Hanaoka

Marie Abe

Toshihiro Tomozaki

Satoru Nishita

Tomoaki Tsuruta

Naohiro Takeda

Nobuyoshi Kawagoe

Shunichi Ihara

In a storage apparatus a control section writes, at the time of updating at least a part of first data stored in a first storage area by at least a part of second data, the second data to a second storage area other than the first storage area. In addition, the control section determines whether or not a write error occurs. When the write error does not occur, the control section combines the first data and the second data.

Storage apparatus, control apparatus, and storage apparatus control method

A bus interface receives, via a bus, a control signal for controlling an electronic circuit, and outputs a signal corresponding to the received control signal to the electronic circuit. A signal maintaining circuit maintains the value of the signal to be output from the bus interface to the electronic circuit in accordance with an instruction from a reset control circuit. When the bus becomes unusable due to termination of operations of the control device or the like, the reset control circuit causes the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently resets the bus interface so as to restore the bus.

Control system for controlling electronic circuit, and signal relaying apparatus

A data communication control device. The data communication control device includes, a controller comprising a first data storing part, the first data storing part including multiple channels, each channel being applied to store a command for data transfer based on a destination of data, the controller executing the command stored in the channel from the head to transfer data and, an overall controller storing the command in the channel of the first data storing part when the number of commands in a certain channel is not over a upper limit, and stopping to store the command in the channel of the first data storing part and creating a second data storing part and storing the command in the second data storing part when the number of commands in a certain channel is over the upper limit.

Data communication control device

A storage control apparatus for transmitting data to and receiving data from a plurality of storage devices connected to the same interface, the storage control apparatus includes a memory configured to store a management table registering a burst transfer length of each of the plurality of storage devices, the plurality of storage devices including a first storage device having a first burst transfer length that is a minimum in the management table and a second device having a second burst transfer length; an adjusting controller configured to adjust the second burst transfer length in input and/or output processing if the second burst transfer length registered in the management table is different from the first burst transfer length; and a data transfer controller configured to issue a command for a data transfer to the second storage device on the basis of the adjusted second burst transfer length.

Storage control apparatus, storage system and method

A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to correspond to the other devices, the channel units retaining DMA transfer instructions, and outputting number of the DMA transfer instructions retained; a plurality of priority controllers for determining priorities of the channel units on the basis of the number of the DMA transfer instructions retained in the channel units, respectively; an arbiter for selecting one of the DMA transfer instructions retained in one of the channel units on the basis of the priorities determined by the priority controller; and a data transfer processor for performing DMA transfer of data stored in the storage unit to one of the other devices in accordance with the DMA transfer instruction selected by the arbiter.

Data transfer device and method for selecting instructions retained in channel unit based on determined priorities due to the number of waiting commands/instructions

In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.

Method of controlling information processing system, information processing system, direct memory access control device and program

In response to a request from a central processing unit (CPU)(i.e., firmware) of a node, a transfer control unitof a direct memory access (DMA) controllertransmits a message and data to another discretionary nodeby way of a serial bus, a switchor the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory. In the case of requesting the transmission of the message, the descriptor contains a flag indicating 'whether or not there is a need to wait for a response from the data transmission destination'. If the flag is set to ON, the transfer control unitnotifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node

DMA controller, node, data transfer control method and storage medium

A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

DMA circuit and computer system

To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.

PCI-express communications system

In a DMA control method in which a DMA controller transfers data in memory to an input/output device in accordance with the control information which is provided by a processing device to a DMA controller, a processing device implements a step in which the processing device sets an information block comprising the control information and the data in the memory; a step in which address information of the information block is provided by the processing device to the DMA controller; a step in which the DMA controller reads the information block from the memory based on the address information and extracts the control information; and a step in which the DMA controller transfers the data in the information block to the I/O device based on the control information.

DMA controller, method, information processing system, and program for transferring information blocks comprising data and descriptors

A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.

Data transfer apparatus by direct memory access controller

A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.

File control system and file control device

A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a DMA engine reads the descriptor from the memory, the DMA engine confirms whether the value is correct, and judges whether a DMA transfer of the data in the memory is possible. For both reading and writing of a descriptor, data corruption due to an address failure can be prevented.

Direct memory access circuit and disk array device using same

To be able to transmit a response packet to a target, which is the original request source node, even if, after issuing a request from a node to another, a bus ID/a device ID is replaced in the PCI-Express switch before said another node makes a response to the request source node in a PCI-Express communication system, which uses a PCI-Express switch. For that purpose, a unique node ID for indicating each node is set to the nodes, a channel ID is set to each channel used for data transfer, and the node ID of the transfer destination module, the channel ID of a channel used for the data transfer, and the packet type indicating that the packet is a request or a response are set in an address field of a packet of data transfer. For the data transfer, only a memory write request packet routed by address routing is used.

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Kawasaki, Japan

Yuichi Ogawa