Mitsubishi Denki Kabushiki Kaisha

Yuichi Nakashima

Hideaki Arima

Yoshinori Okumura

Ikuo Ogoh

Hideki Genjo

Kohjiroh Yuzuriha

Natsuo Ajika

Shinichi Satoh

Hirofumi Shinohara

Takahisa Eimori

Kiyoto Watabe

Hirohisa Yamamoto

Mitsuhiro Tomikawa

Shintaro Matsuda

A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Manufacturing method of an electrically programmable non-volatile memory

A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.

Resin sealed semiconductor device for use in testing and evaluation

A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

Stress reduction structure for a resin sealed semiconductor device

A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Electrically programmable non-volatile memory device and manufacturing

Content addressable memory device

Growing community of inventors

Hyogo, Japan

Yuichi Nakashima