Mitsubishi Denki Kabushiki Kaisha

Yuichi Nakao

Hiroyuki Kondo

Hideharu Toyomoto

Kazumi Koyama

Shunichi Iwata

Toru Shimizu

Shigeo Mizugaki

Yoshio Kasai

Toshio Doi

Toshio Kishi

Naoichi Kitakami

Koji Tsuchihashi

An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Microcomputer for accessing a memory outside the chip by using an

An oscillation stop signal holding latch 3 which stores a value deciding significant/unsignificant of an oscillation stop signal 4, and a NOR gate 21 which controls, when the oscillation stop signal 4 is significant, to stop the generation of a clock signal 7 and controls, when a predetermined signal is inputted from an input terminal 1 of an external signal in the abovementioned states with the oscillation stop signal being unsignificant, to resume the generation of the clock signal 7, and further a sampling circuit 10 between the input terminal 1 of the external signal and the oscillation stop signal holding latch 3 are provided. And a gate circuit 30 which forcibly makes the oscillation stop signal 4 become unsignificant so as to generate the clock signal 7 when the input signal from the input terminal 1 of the external signal is significant is provided. This enables the sampling circuit 10 to sample the input signal from the input terminal 1 of the external signal.

Clock generating circuit for digital circuit operating in synchronism

A digital circuit apparatus having an A/D converter for digitalizing a control voltage which determines the oscillation frequency of an internal clock outputted from a voltage-controlled oscillator, a storing unit for holding a digitalized value, a D/A converter with corrective function for correcting the digital value being held and subjecting the corrected digital value to D/A conversion, and a lock detector for detecting the matching in phase of the internal clock and an external clock. Phase information obtained when the internal clock and the external clock match in phase is held so that, when the generation of the internal clock outputted from the voltage-controlled oscillator is halted and then resumed, the matching in phase of the external clock and internal clock can be achieved in a short period of time.

Digital phase locked loop circuit

A bus controller (20) for a data processing system, in which data is transferred between a bus master (10) and a bus slave (30) of a plurality of different data port sizes, is able to obtain port size information from an address signal using an incorporated address area/port size correspondence table (211), whereby a port size signal as a response signal from the bus slave is made unnecessary, thus simplifying the data processing system.

Bus controller for adjusting port size communication between a bus

A multiplying circuit having sign carry correcting circuits which set all bits of a multiplier Y subjected to sign extension to a certain specific value ('0' or '1'), and when a sign bit, which is the highest bit of effective data in the data to be multiplied, is carried, a specific value signal is input to a bit input portion of a Booth decoder, receiving both the least significant invalid bit and the most significant effective bit of the multiplier, according to a value of a sign extension control signal. In addition, a value inputted to partial product adding circuits from an intermediate result shift circuit is set to a multiplicand value according to the value of a predetermined number of least significant bits of the multiplier, and the multiplier bits excluding the predetermined number of least significant bits inputted to the intermediate result shift circuit are inputted to multiple generating circuits. Thus, a sign extension function or the number of adding circuits to be added in the case of producing a remainder in the number of partial products, at the time of dividing the multiplication into a plurality of operation cycles, are reduced to suppress a circuit scale from becoming larger.

Booth array multiplying circuit having carry correction

A data processor includes an interrupt control unit (102); a direct memory access control unit (103); a selection unit (104) for selecting a connection of ready and error signals from a serial communication control unit and external interrupt and DMA request signals with interrupt inputs to the interrupt and the DMA control units; and a selection setting unit (105) for setting a selection mode of the selection unit, thereby making possible to not only switch between a process by interrupt and a process by DMA transfer by programming according to the application but also make efficient use of the hardware resources in the data processor.

Data processor including selection mechanism for coupling internal and

A wait control device according to the present invention instructs a central processing unit (CPU) to wait for the start of its operation until the device receives a process completion signal from a memory unit or an I/O unit, and comprises setting means for setting the time of said CPU to wait for the start of its operation in the memory unit or the I/O unit accessed by the CPU, judgement means for judging system operation to be time out error when no process completion signal is presented during said time of the CPU, and selector means for selecting whether it passes a signal concerning the judgement of the time out error or successively waits for said processing completion signal.

Wait control device

Bus controller for adjusting a bus master to a bus slave

A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.

Low power consuming digital circuit device

A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.

Refresh control circuit

A direct memory access controller has a data assembly function by means of a single temporary register. This single register used for a number of channels replaces temporary registers which have been necessary for the respective channels to carry out channel transition during data assembly. By controlling channel transition during data assembly, it is possible to carry out DMA transfers in which channel transition is made during data assembly, thereby preventing an increase in the chip size.

Growing community of inventors

Itami, Japan

Yuichi Nakao