Sony Corporation

Thk Co., Ltd.

Sony Semiconductor Solutions Corporation

Saturn Licensing LLC

Yuichi Mizutani

Hideyuki Matsumoto

Hideo Saito

Toshiyuki Miyauchi

Satoshi Okada

Yuichi Hirayama

Tetsuhiro Futami

Naomichi Kishimoto

Atsushi Makita

Takashi Yokokawa

Nobuhiro Hayashi

Kiyoshi Osato

Tadaaki Yuba

Kotaro Kushida

Doan Tien Dung

Sotaro Ohara

Yutaka Nakada

Dung Tien Doan

A transmission device communicates with a reception device via a control data bus in a communication standard of I3C. The transmission device includes a transfer mode switching section and a data transmission section. The transfer mode switching section switches a transfer mode of the control data bus from a first transfer mode having a first transfer rate to a second transfer mode having a second transfer rate faster than the first transfer rate by transmitting a switching command instructing to switch to the second transfer mode after issuance of an IBI request using a function of the I3C in the first transfer mode. The data transmission section transmits data to the reception device via the control data bus in the second transfer mode.

Transmission device and communication system

A communication apparatus includes an IC logic circuit, an I3C logic circuit, an external terminal, and a switch circuit. The IC logic circuit controls communication via a control data bus in accordance with an IC (Inter?Integrated Circuit) communication standard. The I3C logic circuit controls the communication via the control data bus in accordance with an I3C (Improved Inter Integrated Circuit) communication standard. The external terminal is coupled to the control data bus. The switch circuit controls coupling between one of the IC logic circuit and the I3C logic circuit, and the external terminal.

Communication apparatus and communication system

A speed-reducing or -increasing apparatus, with first and second crown gears facing one another, with a cam unit that causes the first crown gear to incline with respect to the second crown gear so that the first crown gear meshes with the second crown gear, that causes the first crown gear to precess in such a manner as to move the meshing position, and couples to an input or output shaft. A rolling element is between the cam unit and the first crown gear, and the cam unit includes a first member that couples to the input or output shaft and a second member made of steel and including a rolling element rolling portion where the rolling element rolls, the second member configured to be incapable of rotating relatively to the first member, and at least part of the first member having a lower specific gravity than the second member.

Speed-reducing or -increasing apparatus

To provide a technology for increasing the speed of sample imaging using a microscope. The present technology provides a flow channel structure including an imaging flow channel in which a fluid containing imaging targets flows in the same direction as the optical axis of an objective lens. The present technology also provides an imaging member including the flow channel structure. The present technology also provides an imaging method that includes imaging an imaging target in an imaging flow channel in which a fluid containing the imaging target flows in the same direction as the optical axis of an objective lens. The present technology also provides an imaging target analysis device and an imaging target analysis system that include the imaging member.

Imaging target analysis device, flow channel structure, imaging member, imaging method, and imaging target analysis system

Provided is a speed reduction or speed increasing apparatus where the rotational stiffness can be increased, including a housing, a first crown gear, a support unit placed radially outward of the first crown gear to support the first crown gear to be capable of wave motion and incapable of rotation with respect to the housing, a second crown gear configured to be rotatable with respect to the housing, the second crown gear having a different number of teeth from the first crown gear, the second crown gear facing the first crown gear, and a cam unit configured to incline the first crown gear with respect to the second crown gear in such a manner that the first crown gear engages with the second crown gear, and to cause the first crown gear to undergo wave motion in such a manner that the location of contact moves.

Speed reduction or speed increasing apparatus

A speed reduction apparatus supports a third crown gear that undergoes wave motion. The speed reduction apparatus includes: a first crown gear; a second crown gear; a third crown gear having opposing teeth facing the first crown gear and opposing teeth facing the second crown gear, back to back; and cam units and that cause the third crown gear to undergo wave motion. The cam units and have a first cam on the first crown gear side with respect to the third crown gear, and a second cam on the second crown gear side with respect to the third crown gear. The first and second cams sandwich the third crown gear. A first rolling element between the first cam and the third crown gear is capable of rolling motion, and a second rolling element between the second cam and the third crown gear is capable of rolling motion.

There is provided a signal processing device including a selection unit that selects and outputs one clock serving as a transport stream (TS) clock, which represents timing of data of a TS, among a plurality of clocks with frequencies not less than a serial rate which is a data rate at which the TS included in a radio frequency (RF) signal is output in a serial manner.

Signal processing device and signal processing method

Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates.

Signal processing device, signal processing method, and program

A data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. A read/write control portion executes read/write control in which slots subject to extraction of two or more slots in one frame that is a collection of two or more slots each of which is a unit of error correction coding are written to a ring buffer and the slots subject to extraction in one frame written to the ring buffer are read within the unit time. When slots subject to extraction are changed, an output portion executes output processing in which dummy data outputted from a dummy data output portion are outputted with a timing immediately before a change start frame that is a frame from which the change of slots subject to extraction is started and, slots subject to extraction read from the ring buffer are outputted for frames subsequent to the change start frame. The present disclosure is applicable to reception apparatuses for receiving BS digital broadcasting, for example.

Data processing apparatus, data processing method, and program

The present disclosure provides a receiver including a demodulation circuit adapted to demodulate data and control information attached to the data, and an extraction circuit adapted to extract some data from entire control information, wherein the demodulation circuit performs demodulation according to the extracted some data.

Receiver, reception method and program

Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.

Receiving apparatus, receiving method and program, and receiving system

A receiving apparatus receives a low density parity check ('LCPC') code and decode the LCPC code to provide for error check capabilities. A bit error rate ('BER') controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.

The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.

Viterbi decoding apparatus

A frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths. A differential correlation detector calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. Frame period confirmation counters perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation countersperform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.

Frame synchronizer, frame synchronization method and demodulator

This invention relates to a demodulating apparatus and a demodulating method for demodulating an input signal more quickly than before when the channels of the input signal are inverted. A correlatorcalculates a correlation value indicative of the correlation between a known delayed detection sequence made of symbols of correct delayed detection values of a known sequence inserted in the input signal and a received delayed detection sequence obtained through delay detection of the input signal. If the imaginary part of the correlation value is less than zero, a channel control sectionswitches the channels of the input signal before feeding the signal to a frame synchronization circuit. This invention can be applied illustratively to a satellite broadcast receiving apparatus.

Growing community of inventors

Tokyo, Japan

Yuichi Mizutani