Asahi Kasei Microdevices Corporation

Yuichi Miyahara

Kazuma Ohara

Takato Katayama

Kanya Sasaki

There is provided an integrator including: a first order delay unit which outputs an output signal obtained by delaying a signal in accordance with an input signal; a first feedback unit which generates a first feedback signal in accordance with the output signal; a second feedback unit which generates a second feedback signal in accordance with the output signal; an addition and subtraction unit which adds and subtracts the first feedback signal and the second feedback signal, respectively, to and from the input signal, for an input to the delay unit; and a control unit which causes the second feedback unit to operate as a delay circuit during the first period, and causes the second feedback unit to operate as a gain circuit having a gain smaller than 0 during the second period.

Integrator and delta-sigma modulator

Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.

Delta-sigma AD converter and delta-sigma AD converting method

Delta-sigma ad converter and delta-sigma ad converting method

An A/D converter includes an incremental delta-sigma A/D modulator and a digital operation unit to which a signal from the A/D modulator is input. The A/D modulator includes an analog integrator configured to integrate input signals, a quantizer configured to quantize output signals of the analog integrator, a D/A converter configured to D/A convert an output of the quantizer, and a reset signal output device configured to reset the analog integrator and the digital operation unit. The analog integrator includes plural switched capacitors and a first analog integrator connected to the switched capacitors. The first analog integrator includes an operational amplifier connected to the switched capacitors and a feedback capacitor each connecting an input and an output of the operational amplifier.

Incremental delta-sigma A/D modulator and A/D converter

There is provided a pipelined A/D converter in which plural stages Stageto Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP () included in the MDAC for the SPM, MOS transistors (Mx) and (Mx) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My) and (My) as a load unit connected to the differential pair, a current source (I) configured to supply a current to the MOS transistors (Mx) and (Mx) as the differential pair, and current sources (I) and (I) configured to adjust the current flown across the MOS transistors (My) and (My) as the load unit.

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Tokyo, Japan

Yuichi Miyahara