Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Yuichi Matsushita

Norihiko Satani

Kenji Satou

Akira Nakayama

Shizuo Cho

Takahiro Imayoshi

Tetsuya Mitoma

Toshiro Sasaki

Kenji Sato

In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

Semiconductor circuit and method of retrieving signal to semiconductor circuit

A differential amplifier formed on a silicon-on-insulator substrate, including means to prevent the bodies of its differential input transistors from charging to unwanted potentials in the standby state. In one aspect of the invention, the means takes the form of switching transistors inserted between the differential input transistors and their loads. In another aspect of the invention, the means takes the form of switching transistors inserted between the sources and bodies of the differential input transistors. In another aspect of the invention the means is a regulator section that holds the bodies of the differential input transistors at an appropriate potential level.

Silicon-on-insulator differential amplifier circuit

The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node) when the output stays in low, for discharging the stored charge of nodewhen the output stays in high, a comparator (C) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuitfor controlling the discharge current based on constant current.

Pulse width modulation circuit

A voltage regulator has a reference voltage generator that outputs a reference voltage based on first and second electrical source voltages, an output circuit which generates a predetermined direct-current voltage based on the reference voltage and generates a comparison voltage lower than the predetermined direct-current voltage, and a differential amplifier coupled between the reference voltage generator and the output circuit. The differential amplifier provides a control voltage to the output circuit responsive to a difference between the reference and comparison voltages. The voltage regulator has a voltage adjustment circuit that adjusts the reference voltage responsive to a variation in the first electrical source voltage. The differential amplifier may include a constant-current circuit and an operation current generating circuit. The voltage regulator may include a detecting circuit that detects a variation in the first electrical source voltage and controls the operation current generating circuit responsive thereto.

Voltage regulator which outputs a predetermined direct-current voltage with its extreme variation restrained

A start-up circuit includes a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is coupled between the first node and the ground node, a supply circuit which is coupled between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is coupled between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.

Start-up circuit

The present invention implements a decrease in chip size. The device is comprised of memory cell arrays,and,, a bank selector,a cell select circuit,a data multiplexer,and an input/output buffer,The bank selector generates a bank select signal and selects the memory cell arrays alternately. The cell select circuit selects a predetermined memory cell of the memory cell array selected by the bank select signal and performs a read operation from and a write operation to this memory cell. The data multiplexer transfers the read data from the memory cell array selected by the bank select signal to the input/output buffer.

Semiconductor storage device

A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal voltage applied to an input terminal. The first capacitor is discharged to boost the voltage at a boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an &ldquo;H&rdquo; level to an &ldquo;L&rdquo; level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor. The voltage at the boosting node is boosted by the discharge of the first capacitor, and the output terminal and the source voltage are coupled by a transistor that is activated in response to the boosted voltage at the boosting node. It is thus possible to increase the voltage at the output terminal to the source voltage V,.

Booster circuit

A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost a voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an &ldquo;H&rdquo; level to an &ldquo;L&rdquo; level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor. The voltage at the boosting node is boosted by the discharge of the first capacitor, and the output terminal and the source voltage are coupled by a transistor that is activated in response to the boosted voltage at the boosting node. It is thus possible to increase the voltage at the output terminal to the source voltage V,.

A column switching circuit that connects a bit line pair and sub-data buses is constituted of first through fourth N transistors. The first and third N transistors are connected in series to a first bit line of the bit line pair whereas the second and fourth N transistors are connected in series to the second bit line of the bit line pair. The gate of the first N transistor and the gate of the second N transistor are connected to commonly receive a column switch selection signal. The gate of the third N transistor and the gate of the fourth N transistor are commonly connected to a column line. By adopting this structure, the generation of a through current is prevented from occurring between the bit line pair and the sub-data buses to result in a reduction in power consumption and miniaturization of the chip is achieved.

Semiconductor memory device having a common column decoder shared by

A semiconductor device includes plural fuse wiring paths which extend substantially parallel to each other in a first direction, each of the fuse wiring paths having a fuse element. A normal column line extends in a second direction substantially perpendicular to the first direction, the normal column line corresponding to a normal memory cell which stores data. The semiconductor memory device further includes a redundant column line extending in the second direction, the redundant column line corresponding to a redundant memory cell which stores data. A logic circuit receives respective signals on the plural fuse wiring paths, and outputs a selection signal according to these signals. The semiconductor device also includes a switching circuit coupled between the logic circuit and the normal and redundant column lines, which receives an address signal and the selection signal, and which selectively transfers the address signal to the normal column line or the redundant column line in response to the selection signal.

Semiconductor device

There is provided a semiconductor memory device 100 comprising memory cell blocks 20-1 to 20-n, decoder circuits 10-1 to 10-n that carry out the redundant operation provided so as to correspond to each memory cell block, a Roll Call signal transmission circuit 110 which detect if the redundant function is in operation; wherein each decoder circuit outputs a decoder signal FCi at low level to the Roll Call signal transmission circuit when the redundant function is in operation, but outputs a decoder signal at high level when the redundant function is not in operation, and wherein the Roll Call signal transmission circuit outputs a judgment signal at high level when all the decoder signals are at high level, but outputs a low level judgment signal when any of the decoder signals is at low level.

Semiconductor memory device

A redundant semiconductor memory capable of functioning normally on the whole even if two column (or row) lines do not function normally. The semiconductor memory includes primary and secondary selection circuits, primary and secondary switchover circuits, and (N+2) memory cell groups. The primary switchover circuit receives a decoded address signal of N bits for selecting one memory sell group, and outputs to the secondary switchover circuit a signal of (N+1) bits which is generated by inserting a bit into a position of the inputted decoded address signal specified by the primary selection circuit. The secondary switchover circuit outputs to the memory cell groups a signal of (N+2) bits which is generated by inserting a bit into a position of the inputted signal specified by the secondary selection circuit.

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Miyazaki, Japan

Yuichi Matsushita