Nec Corporation

Nippon Electric Co., Ltd.

Yuichi Kawakami

Takao Nishitani

Hideo Tanaka

Ichiro Kuroda

Kohji Doi

In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data. A calculation performing circuit (20) is for performing a predetermined calculation on the pair of read data by using a coefficient read from a read-only memory (14) to produce a pair of calculated data which are stored in the first and the second addresses as the stored data. The calculation performing circuit performs the predetermined calculation a plurality of times to produce the output elements.

Signal processor for rapidly calculating a predetermined calculation a

In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.

Processing circuit capable of raising throughput of accumulation

A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a '0' bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.

Double precision multiplier

A digital circuit for executing an arithmetic operation includes an overflow processing capability. The overflow processing is performed by a shifter to correct a decimal point. The shifter is used to shift a result of the arithmetic operation with an overflow and to shift a data to be operated by an arithmetic unit. The result and the data are applied to the shifter via a multiplexer, and either one of them is transferred to the shifter. The shifter is controlled such that the result of the arithmetic operation is shifted by one bit, while the data is shifted according to the number of overflows. As the result, the digital circuit can perform an arithmetic operation at a high speed by means of a simple hardware element.

Digital circuit performing an arithmetic operation with an overflow

Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.

Arithmetic circuit with overflow detection capability

An improved random access memory permits non-CPU involved, direct access for data read out to a portion of memory - as for information display purposes. The composite memory (and thereby also apparatus employing such a memory) may thus be more readily and inexpensively fabricated, not requiring either a dedicated, separate display register or stored instructions for memory-to-display register information transfer. The memory includes first and second portions each capable of central process or access, the second memory segment being subject to direct, non-CPU aided addressing when not engaged by the CPU.

Growing community of inventors

Tokyo, Japan

Yuichi Kawakami