Fujitsu Corporation

Tii Industries, Inc.

Yuichi Kawabata

Toshitaka Fukushima

Kazumi Koyama

Kouji Ueno

Tamio Miyamura

Raymond D Jones

John Napiorkowski

An output buffer circuit capable of three-output states of high and low levels and a high impedance. The output buffer circuit includes a detector circuit for detecting that a power source voltage for the buffer circuit is particularly high and for turning the output of the buffer circuit to the high impedance state when the high voltage is detected.

Tristate output buffer with high-impedance state responsive to increase

A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.

Semiconductor memory device

A PROM device having the improved bit address decoders composed of a plurality of AND gates, each of the AND gates comprising PNP type transistors, to each base of which is applied an address signal from the bit address inverters. Each collector of these transistors is connected to ground, and each emitter is connected to the output terminal of the bit address decoder.

Programmable read-only memory device

A program circuit for permanently storing data into a programmable read only memory. A programming current (received from an external source) is connected to the selected bit line through a Darlington pair which is controlled by the bit decoding circuitry. Thus, the bit decoding circuitry is not required to pass the large programming current, and the programming current is not significantly shunted away from the selected bit line. To facilitate use of the Darlington configuration, a constant current source is provided for each bit line within a set of bit lines. The program circuit includes at least one switching means for connecting the program current to a selected bit line, a bit decoder connected to the control inputs of the switching means for selecting a bit line in response to the addressing signals input to the bit decoder and a control current supplying means for supplying a control current to the control inputs of the switching means.

Programming circuit for permanently storing data in a programmable read

A screw-in station protector assembly includes a carrier housing containing a shorting cage which is biased by a compression to urge the cage and gas tube arrester assembly outwardly. The gas tube assembly contained within the cage includes a two electrode gas tube. The gas tube is within a jacket which forms a sealed external back-up air gap protector. The screw-in-assembly is particularly adapted for retro-fitting/replacement of carbon block arresters without modification.

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Kawasaki, Japan

Yuichi Kawabata