Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Yuichi Hirofuji

Yasushi Naito

Hiroyuki Sakai

Tsutomu Fujita

Haruyasu Yamada

Kazuhiro Yamashita

Toyoki Takemoto

Hiroshi Sakoh

Tadao Komeda

Yutaka Nabeshima

Mitsuo Yasuhira

Mototsugu Ogura

Keiichi Kagawa

Norisato Shimizu

Yutaka Ito

Haruhisa Yokoyama

A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.

Solid-state imaging device

A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.

Semiconductor device

The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions

Method of fabricating a high-density dynamic random-access memory

A first underlaid oxide layer, a polysilicon layer, and a first silicon nitride layer are formed on a silicon substrate in this order. Using a photoresist as a mask, a portion of the first silicon nitride layer, the polysilicon layer, the first underlaid oxide layer and the silicon substrate which is to be an isolation region is etched by a depth which regulates a length of bird's beak and a threshold voltage drop of a FET adequately. After forming a second underlaid oxide layer and a second silicon nitride layer, silicon nitride side walls of more than 25 nm in thickness are formed. An isolation oxide layer is formed by selective oxidation, using the silicon nitride layer as a mask. Favorable etched depth in the step of removing the silicon substrate is one third of the thickness of the isolation oxide layer. Favorable etched depth in case of a normal FET is 20-100 nm. Thus, bird's beak length is reduced, while adequately maintaining the threshold of the transistor at formation of the isolation of transistor. In a DRAM cell pattern, isolation of not exceeding 0.2 .mu.m width can be formed.

Method of forming isolation

A flow passage into which water-to-be-treated flows is provided with, in order from an upstream side, a deaerator as a DO eliminating device having a power variable mechanism, an oxidation device for oxidizing TOC by irradiating ultraviolet-ray, an ion eliminating device for eliminating TOC ion generated at oxidation, and a particle eliminating device. Further provided thereat are a TOC density measuring device, a DO density measuring device and a data processing device. Before the water-to-be-treated is irradiated with ultraviolet-ray in the TOC eliminating device (oxidation device and ion eliminating device), the deaerator controls a DO density in the water-to-be-treated according to a TOC density. Thus, an oxidizer of the TOC is maintained and impurity is decreased.

Device and method of producing pure water

Semiconductors are treated with such surface-treating solutions as ultra-pure water, dilute hydrofluoric acid and an organic solvent and then subjected to removal of the surface-treating solutions remaining on the surface of the semiconductor in an inert gas atmosphere of high purity while contacting the surface of the surface-treated semiconductor only with the inert gas of high purity, whereby contamination with impurities on atom level from the atmosphere can be prevented.

Process for treating semiconductors

In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

Growing community of inventors

Osaka, Japan

Yuichi Hirofuji