Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Samsung Electronics Co., Ltd.

Renesas Technology Corp.

Yuichi Hirano

Shigenobu Maeda

Toshiaki Iwamatsu

Yasuo Yamaguchi

Takashi Ipposhi

Shigeto Maegawa

Ha-Young Kim

Sung Chul Park

Chul Hong Park

Sung Min Kang

Ji Wook Kwon

Yoshinao Harada

A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Semiconductor device

A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.

Semiconductor device and manufacturing method thereof

Semiconductor device including monos-type memory cell

A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.

Semiconductor device with transistors having different source/drain region depths

a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the first layer.

Semiconductor device and method for producing the same

A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film ( ) is formed by oxidizing an edge section and a lower major surface of an SOI substrate ( ). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film ( ) exposed on the edge section and lower major surface of the SOI substrate ( ) as an underlying oxide film. Then, the thickness of the oxide film ( ) is greater than that of the oxide film ( ) on the edge section and lower major surface of the SOI substrate ( ). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

Semiconductor substrate and method of fabricating semiconductor device

An FS upper nitride film (,) is formed on the upper surface of an FS electrode (,). Therefore, the upper surface of the FS electrode (,) is not exposed even when an FS upper oxide film (,) is partially almost removed in the manufacturing process. Thus, a semiconductor device which prevents degradation in operation characteristics and reliability due to existence of an FS insulating layer can be provided.

Semiconductor device with field shield electrode

A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

Growing community of inventors

Kanagawa, Japan

Yuichi Hirano