Hitachi, Ltd.

Hitachi-High-Technologies Corporation

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Yuichi Hamamura

Aritoshi Sugimoto

Akira Shimase

Hidemi Koike

Kazuyuki Tsunokuni

Junzou Azuma

Hisao Asakura

Takaaki Kumazawa

Yuji Takagi

Michinobu Mizumura

Seiji Isogai

Satoshi Tomimatsu

Tohru Ishitani

Kenji Watanabe

Yasuhiko Ozawa

Atsushi Shimoda

Takuo Tamura

Yasuhiro Koizumi

Isamu Sekihara

Junzo Azuma

Norimasa Nishimura

Ichirou Ishimaru

Minoru Harada

Seiji Ishikawa

Yasunori Yamaguchi

Shigenori Tanaka

Katsuhiko Ichinose

Tomohiro Funakoshi

Kei Imazawa

Yutaka Tandai

Natsuyo Morioka

Tsunehiro Sakai

Tamao Ishikawa

Chizu Matsumoto

Shigeki Kurihara

Isamu Momose

Yusaku Fukaya

Yoshiyuki Tsunoda

Kouichirou Tada

Katsumi Ikegaya

Kazuo Ito

A method for work quality control of a worker in work where repetitive operation is performed which includes: a model construction step of statistically constructing, from past path data of the worker, past intermediate quality data on a product to be subjected to the work, and past final quality data on the product to be subjected to the work, a prediction model that receives the path data and the intermediate quality data and outputs the final quality data; a worker position recognition step of recognizing a position of the worker from image data on the work captured; and an unusual worker position determining step of substituting the position of the worker recognized in the worker position recognition step into the model constructed in the model construction step, to determine whether the position of the target worker is a usual one or an unusual one.

Method and apparatus for work quality control

A defect image processing apparatus uses a normalized cross correlation to image-match a layout image () acquired from a design data with an image acquired by removing, from a defect image (), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image () on the display device. In the displayed layout image & defect image (), not only the layout image, the layer of which is the same as that of the defect image (), but also a layout image of another layer is displayed superimposed on the defect image (). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method

The present invention relates to semiconductor inspection and provides a technology capable of efficiently detecting a systematic defect. In the present system, with regard to the process (S, S) of matching hot spot (HS) points that can be simulated in advance and defect points obtained as a result of a visual inspection each other and the unmatched defect points, a process (S, S) of classifying the defect points into groups based on similarity of pattern layout at the defect points to determine the defects belonging to a pattern layout where defects frequently occur, thereby reliably detecting the systematic defect. Also, with a process (S) of acquiring an uneven distribution in a defect occurrence distribution on a wafer, the systematic defect occurring due to topography of the wafer can also be detected.

Reviewed defect selection processing method, defect review method, reviewed defect selection processing tool, and defect review tool

In order to enable an evaluation of systematic defects, a method of evaluating systematic defects was configured so as to sample a circuit pattern of a specific layer of a semiconductor device, evaluate the state of superimposition between the sampled circuit pattern and circuit patterns of layers other than the specific layer, using design data, classify the state of superimposition, calculate the ratio thereof as a reference ratio, evaluate the state of superimposition between a pattern in design data corresponding to a defect of the specific layer detected by another inspection apparatus and patterns at positions corresponding to the defects in layers other than the specific layer, classify the evaluated state of superimposition, calculate the ratio of the classification as inspection-result ratio, compare the calculated reference ratio and the calculated inspection-result ratio, and evaluate systematic defects by the comparison between the calculated reference ratio and the calculated inspection-result ratio.

Method of evaluating systematic defect, and apparatus therefor

In a managing system for a semiconductor manufacturing apparatus, a predicting unitpredicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device

An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.

Semiconductor device yield prediction system and method

A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.

Method for analyzing circuit pattern defects and a system thereof

A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow () appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.

Probe driving method, and probe apparatus

In order to allow critical flaws in an inspected item to be determined early during a production process, the present invention includes the following steps: a step of detecting defects in a production process for the inspected item and storing defect positions; a step of collecting detailed defect information and storing the detailed information in association with defect positions; a step of storing positions at which flaws were generated based on a final inspection of the inspected item; a step of comparing defect positions with positions at which flaws were generated; and a step of classifying and displaying detailed information based on the comparison results.

Method and system for analyzing circuit pattern defects

A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.

A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

Growing community of inventors

Yokohama, Japan

Yuichi Hamamura