Motorola Corporation

Yui K Ho

William C Moyer

Joseph A Gutierrez

Claude Moughanni

Grady L Giles

Robert Bradford Cohen

Pee-Keong Or

A method and apparatus for performing a cache operation in a data processing system (10). In one form, the present invention has a 'block address translation cache (BATC) only mode' in which a received logical address is compared to the logical addresses stored in only one of a plurality of address translation caches, i.e. the block address translation cache (BATC) (76). The overhead associated with loading and comparing one or more other caches (78) is not incurred. If the comparison with that one cache (BATC) (76) produces a hit, that cache (BATC) (76) supplies the address that is used as the physical address. If the comparison with that one cache (BATC) (76) produces a miss, then a 1:1 mapping is used and the received logical address is used as the physical address.

Method and apparatus for performing a cache operation in a data

A data processing system (20) allows a user of a pager to receive an electronic message in a language of their own choice rather than the language of a message sender. During operation, the data processing system is enabled to receive (12) an incoming message and, subsequently, detect a language of the incoming message. If the language is different than a default language of the user, the message is translated to a default language of the user (34). The message is then be displayed (40) on a screen of a paging device in the language preselected by the user or provided via a voice synthesizer (50) for an audio message. The choice of use of a visual display or use of the voice synthesizer is preselected by the user.

Language translating pager and method therefor

A wireless paging device (10) is able to control an electronic device (50) at a remote location. The wireless paging device includes a receiver (12) such as those typically used in pagers to detect when a particular electronic device is being remotely accessed. If the electronic device is being remotely accessed, a data processing system (20) stores an incoming message in a buffer (24) and subsequently determines if the incoming message is a command or another type of communication (34, 36). The data processing system will process a command to provide the proper control signals for controlling the functionality of the electronic device (50).

Pager for wireless control and method therefor

A method and apparatus for accessing a register in a data processing system (10). In one form, the present invention uses a storage circuit (23) to act as a register copy (23) of the original register (33). An access to the register location may actually selectively access the original register (33), the register copy (23), or both the original register (33) and the register copy (23). Register select logic (70) is used to perform this selection function. Register select logic (70) may also be used to keep track of the current status of the contents of the original register (33) and of the contents of the register copy (23). Register select logic (70) may also monitor the internal state of data processing system (10).

Method and apparatus for accessing a register in a data processing system

A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20, 44, 48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).

Data processor with combined static and dynamic masking of operand for

A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.

Data processor with concurrent static and dynamic masking of operand

A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20,44,48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).

Data processor with shared control and drive circuitry for both

An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is identical to information previously stored in the system. However, the Match line signal associated with the predetermined row is disabled by a predetermined transistor (14, 16, 18, 20) when the row is written. Because information is simultaneously presented in parallel to other rows in the CAM system, a Match line signal is asserted if the information currently written to the predetermined row is identical to information previously written to another row in the CAM system. Any asserted Match line signal which was not disabled indicates to the user of the CAM system that two or more entries are identical in the CAM array.

Growing community of inventors

Austin, TX, United States of America

Yui K Ho