Cadence Design Systems, Inc.

Yuhua Yang

Peng Zhang

Nan Zhuang

An apparatus and method are provided for removing redundant logic in a logic design of an integrated circuit (IC) design. The apparatus and method optimizes the integrated circuit by selecting stuck-at constant registers in the logic design, propagating a constant output value of the stuck-at constant registers across output nets of the stuck-at constant registers, identifying redundant logic in the logic design based on the propagation of the constant input value across the output net of the stuck-at constant register, and removing the redundant logic in the logic design.

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Yuhua Yang