Qualcomm Incorporated

Yuhua Guo

Dinesh Jagannath Alladi

Lei Sun

Elias Dagher

Seyed Arash Mirhaj

Wei Zheng

Chieh-Yu Hsieh

Anand Meruva

Yongjian Tang

Lai Kan Leung

Yan Wang

Timothy Donald Gathman

Liang Dai

Masoud Roham

Omid Rajaee

Balasubramanian Sivakumar

Aram Akhavan

Masoud Ensafdaran

Xiaopeng Zhong

ChienChung Yang

A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

Analog-to-digital converter having time-constant tuning with pulse-width-based reference current and resistance searching

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

Pipelined analog-to-digital conversion

Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC)

A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

Time-interleaved charge sampler receiver

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Calibration for time-interleaved analog-to-digital converters and signal generators therefor

Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.

Charge sharing linear voltage regulator

Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

Low noise and low power passive sampling network for a switched-capacitor ADC with a slow reference generator

Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

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San Diego, CA, United States of America

Yuhua Guo