Sharp Kabushiki Kaisha Corporation

Yuhichiroh Murakami

Yasushi Sasaki

Shige Furuta

Seijirou Gyouten

Makoto Yokoyama

Etsuo Yamamoto

Hajime Washio

Shuji Nishi

Takahiro Yamaguchi

Eiji Matsuda

Sachio Tsujino

Hidekazu Yamanaka

Shinsaku Shimizu

Hiroyuki Ohkawa

Hiroyuki Adachi

Kohei Hosoyachi

Keiichi Ina

Shunsuke Hayashi

Takuya Hachida

Noboru Matsuda

Kazuhiro Maeda

Michael James Brownlow

Yasuyoshi Kaise

Junichi Yamada

Satoshi Fujii

Kenji Hyodo

Osamu Sasaki

Shinya Takahashi

Hiroshi Murofushi

Mamoru Onda

Kenji Hyoudou

A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Active matrix substrate and display device including the same

A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Display device using binary driver having several holding circuits

The display device includes, on a substrate, a plurality of pixel electrodes, M (M is a natural number equal to or greater than three) counter electrodes disposed opposite the plurality of pixel electrodes, M counter electrode wiring lines connected with M counter electrodes, and N (N is a natural number and 2&#x2264;N&#x3c;M) common voltage wiring lines connected to the M counter electrode wiring lines. Counter electrode wiring lines connected to counter electrodes adjacent to each other are connected to common voltage wiring lines that are different from each other.

Display device

A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Data signal line drive circuit and liquid crystal display device provided with same

A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area is changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.

Active matrix substrate and display device

An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.

Active matrix substrate and display panel

Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T, T, T) whose on-off state is controlled at relatively high on-duty and a second group (T, T, T, T, T, T) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.

Shift register circuit

A unit circuitof a shift register is provided with a transistor Trfor supplying an off potential to a node nvia a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Trdoes not turn on and charge does not escape from the node. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.

Shift register

A unit circuitof a shift register is provided with a transistor Trhaving a drain terminal connected to a node N, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N. The unit circuitis further provided with a transistor Trhaving a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node Nto be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Trbefore the initialization.

The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL(i&#x2212;1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer () makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line(i&#x2212;1)+k via a correction capacitance element (Cc). The inversion delayer () makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

Data signal line drive circuit, data signal line drive method and display device

A shift register according to the present invention is a shift register in which a plurality of unit circuits are connected in cascade, wherein the unit circuit includes a first output transistor whose current path is connected between an output terminal and a clock terminal to which a first clock signal is provided; a second output transistor whose current path is connected between the output terminal and a predetermined potential node; a setting device which, when a control signal is active, sets a signal level of the output terminal to a predetermined signal level; a first output control device which provides a signal level of the control signal to a control electrode of the first output transistor to turn off the first output transistor when the control signal is active; and a second output control device which turns off the second output transistor when the control signal is active.

Shift register and display apparatus

A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal. The shift direction is switched by changing the generation order of pulses of clock signals.

A demultiplexer circuit () of a display device according to one aspect of the present invention includes signal input lines (Vn), control lines (BSW, GSW, and RSW), and sampling transistors (RG, andB). Sampling transistors connected to one signal input line includes first and second sampling transistors. A first sampling transistor (B) includes a control electrode () which branches to a first branch part () and a second branch part (), either one of an input electrode () and an output electrode () that are disposed between a first branch part () and a second branch part (), and other one of an input electrode () and an output electrode () that are disposed outside of a first branch part () and a second branch part ().

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Trswitches between whether or not to provide an output of an on-potential output unitto a gate terminal of Trin accordance with an output of a set control unit. The set control unitcontrols a gate terminal of Trinto a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr. The gate potential of Tris raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

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Osaka, Japan

Yuhichiroh Murakami