Sharp Kabushiki Kaisha Corporation

Yuhichi Saitoh

Hiroaki Furukawa

Atsushi Hachiya

Tomohisa Aoki

Yohsuke Kanzaki

Tetsuya Okamoto

Yoshiki Nakatani

Yudai Takanishi

Tohru Okabe

Hirohiko Nishiki

Yasuaki Iwase

Masao Moriguchi

Mayuko Sakamoto

Tokuo Yoshida

Shogo Murashige

Yosuke Kanzaki

Izumi Ishida

Yujiro Takeda

Shinji Nakajima

Hirohide Mimura

A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.

Display device and method of manufacturing display device

An oxide semiconductor layer includes a second channel region and a second conductor region. The lower metal layer includes a contact wire in contact with the second conductor region. The upper metal layer includes an upper wire. A second interlayer insulating film is provided with a second contact hole overlapping an upper wire and the contact wire. The second conductor region and the upper wire electrically connect together through the contact wire.

Display device having a first transistor including a crystalline silicon semiconductor layer and a second transistor including an oxide semiconductor layer

A crystalline silicon semiconductor layer includes a first channel region and a second conductor region. An oxide semiconductor layer includes a second channel region and a second conductor region. An lower metal layer includes a lower wire. The lower wire is in contact with a first conductor region in a first contact hole. The first conductor region and the second conductor region are electrically connected together through the lower wire.

Display device

One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.

Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500&#xb0; C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.

Method for manufacturing semiconductor device and film forming apparatus

An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.

Active matrix substrate and display device

An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.

Active matrix substrate and demultiplexer circuit

A semiconductor device includes a lower wiring layer formed on a substrate; a lower insulating layer formed on the lower wiring layer; an upper wiring layer formed on the lower insulating layer, the upper wiring layer intersecting with the lower wiring layer across the lower insulating layer to form a wiring cross portion; and an island-shaped upper insulating layer formed on the lower insulating layer so as to be in contact with the upper wiring layer, wherein the upper wiring layer includes a first portion formed on the upper face of the lower insulating layer and a second portion disposed on the wiring cross portion and formed on a side wall of the upper insulating layer, and wherein the upper wiring layer is not formed on the upper face of the upper insulating layer at the wiring cross portion.

Semiconductor device and method for manufacturing same

A semiconductor device includes a substrate; a gate electrode provided on the substrate; a first insulating layer formed on the gate electrode; an island-shaped oxide semiconductor layer formed on the first insulating layer; a source electrode electrically connected to the oxide semiconductor layer; and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first insulating layer has a recess in the surface, wherein the oxide semiconductor layer is formed on a bottom surface and side walls of said recess and on an upper face of the first insulating layer, and wherein at least one of the source electrode and the drain electrode is disposed on a portion of the oxide semiconductor layer over the side walls of said recess, and is not formed on a portion of the oxide semiconductor layer over the upper face of the first insulating layer.

The present invention provides a semiconductor device which is provided with an oxide semiconductor TFT that can be reduced in the parasitic capacitance by suppressing process damage to a channel, while reducing the channel length (L). A semiconductor device of the present invention is provided with: a gate electrode () that is provided on a substrate (); a first insulating layer () that is formed on the gate electrode (); an island-shaped oxide semiconductor layer () that is formed on the first insulating layer (); a source electrode () and a drain electrode () that are electrically connected to the oxide semiconductor layer (); and a protective layer () that covers the upper surface of the oxide semiconductor layer (). The source electrode () and/or the drain electrode () is arranged on a portion of the side faces of the oxide semiconductor layer () and a portion of the side faces of the protective layer (), but does not cover the upper face of the protective layer ().

A TFT substrate () includes a plurality of pixel electrodes () provided in a matrix, a plurality of TFTs () each provided for a corresponding one of the pixel electrodes (), and a plurality of auxiliary capacitors () each provided for a corresponding one of the pixel electrodes (). Each of the auxiliary capacitors () includes a capacitor line () made of a material identical to that of the gate electrode () of the TFT () and provided in a layer identical to that of the gate electrode () of the TFT (), the gate insulating film () provided so as to cover the capacitor line (), and a corresponding one of the pixel electrodes () provided on the gate insulating film () so as to overlap with the capacitor line () and being in conduction with a drain electrode ().

Thin film transistor substrate, method for manufacturing the same, and liquid crystal display panel

An active matrix substrate of the present invention includes: data signal lines; scanning signal lines (GLi); transistors connected with the data signal lines and the scanning signal lines (GLi); and retention capacitor lines (CSLi). One pixel region includes a plurality of pixel electrodes. A CS driver () for outputting a retention capacitor line signal to drive the retention capacitor lines is formed monolithically. In one pixel region, a pixel electrode and a retention capacitor line corresponding to the pixel electrode forms a retention capacitor therebetween. This allows the liquid crystal display device based on a pixel-division system to have a liquid crystal panel with a narrower frame.

Active matrix substrate, liquid crystal panel, liquid crystal display device, television receiver

In a liquid crystal display device in which one pixel is divided into the plurality of subpixels, a narrow picture-frame is realized by decreasing a wiring region without reducing a display quality. One of two sub-pixel portions includes a second transistor (TB) having a gate connected to a first scanning signal line (GL) and having a source connected to a data signal line (SL), a pixel electrode (EB) connected to a drain of the second transistor (TB), a liquid crystal capacitance (ClcB) formed by a common electrode () and the pixel electrode (EB), a third transistor (TC) having a gate connected to a second scanning signal line (GL) and having a source connected to a line SEL, a capacitance electrode (EC) connected to a drain of the third transistor (TC), and a capacitance (Cl) formed by the pixel electrode (EB) and the capacitance electrode (EC). A high potential and a low potential are alternately provided to the line SEL for each one frame. The second scanning signal line (GL) is selected after the first scanning signal line (GL) is selected.

Liquid crystal display device with potential varying capacitance electrode

An auxiliary capacitor () includes a capacitor line (), a gate insulating film () provided so as to cover the capacitor line (), a semiconductor layer () provided on the gate insulating film () so as to overlap with the capacitor line (), and a drain electrode () provided on the semiconductor layer () and connected to a pixel electrode (). The semiconductor layer () made of an oxide semiconductor and the pixel electrode () made of an oxide conductor contact each other.

A semiconductor deviceaccording to the present invention includes an active layersupported on a substrateand having two channel regions, a source region, a drain region, and an intermediate regionformed between the two channel regions; a contact layerhaving a source contact region, a drain contact region, and an intermediate contact region; a source electrode; a drain electrode; an intermediate electrode; and a gate electrodefacing the two channel regions and the intermediate region through a gate insulating filminterposed therebetween. An entire portion of the intermediate electrodethat is located between the first channel regionand the second channel regionoverlaps the gate electrodethrough the intermediate regionand the gate insulating film

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Osaka, Japan

Yuhichi Saitoh