Sandisk Technologies Inc.

Sandisk 3d LLC

Western Digital Technologies, Inc.

Yuheng Zhang

Luca Giovanni Fasoli

Gopinath Balakrishnan

Yan Li

Tz-Yi Liu

Hao Su

Daniel Lee Helmick

Po-Shen Lai

Mai Ghaly

Jeffrey Koon Yee Lee

Yibo Yin

Chandan Mishra

Kent Douglas Anderson

Pao-Ling Koh

Amir Hossein Gholamipour

James B Hart

Gordon Yee

An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Pre-computation of memory core control signals

An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

Efficient control of memory core circuits

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.

Microcontroller for non-volatile memory with combinational logic

Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

Error reducing matrix generation

Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

Data availability during memory inaccessibility

A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

Systems and methods for on-die control of memory command, timing, and/or control signals

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Program cycle skip

A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

Page buffer program command and methods to reprogram pages without re-inputting data to a memory device

A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.

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Saratoga, CA, United States of America

Yuheng Zhang