Xiamen Tianma Display Technology Co., Ltd.

Xiamen Tianma Micro-electronics Co., Ltd.

International Business Machines Corporation

Intel Corporation

Shanghai Tianma Micro-electronics Co., Ltd.

Marvellworld Trade Ltd.

Shanghai Tianma Am-oled Co., Ltd.

Yuheng Zhang

Jieliang Li

Wanming Huang

Xiao Feng Guan

Yu Xuan Zhang

Yong Yuan

JiuFu Guo

Travis T Schluessler

Feng Lu

Feng Chen

Li Xu

Sen Lin

Jiu Fu Guo

Haihao Xiang

Jiemiao Pan

Qijun Yao

Qing Feng Zhang

Lihua Wang

Yingteng Zhai

Liang Liu

Conghua Ma

Jin Song Ji

Shui He

Shaolong Ma

Si Yuan Zhang

Kang Ed Zhang

Jinjin Yang

Haitao Huang

Ke Wen Lin

Liping Gao

Xinyu Qi

Zaiwen Zhu

Jinsong Ji

Pengfei Qiu

Ningsheng Jian

Qitai Ji

Xiangyuan Li

Shengchao Ji

Xiaoting Xing

Yi Zeng Mao

Zi Xuan Wu

Xueqi Sun

A display panel includes a pixel circuit including a driving transistor, a driving circuit configured to provide a control signal to the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. The pixel circuit further includes a first transistor and a second transistor. The driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor. The clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit.

Display panel and display device

A display panel includes a pixel circuit including a driving transistor, a driving circuit configured to provide a control signal to the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1 in at least one stage of the N stages. When the pixel circuit is operated in the holding stage, the clock pulse frequency of the clock signal is a second frequency F2 in at least one stage of the N stages, the clock pulse frequency of the clock signal is a third frequency F3 in at least one stage of the N stages. F1>F2>F3≥0.

Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. In a data writing phase, a data writing module of the pixel circuit provides a data signal. In an initialization writing phase, an initialization module of the pixel circuit provides an initialization signal. In the same data writing frame, a time period between the start time of the initialization writing phase and the start time of the data writing phase is an initialization phase. The duration of the initialization phase in a first mode is different from the duration of the initialization phase in a second mode, and/or the duration of the initialization writing phase in a first mode is different from the duration of the initialization writing phase in a second mode.

A display panel includes a pixel circuit and a light-emitting element. The working process of the pixel circuit includes a data write stage and a bias stage. The working process of the pixel circuit includes a first light emission stage and a first non-light emission stage. In the first non-light emission stage, a bias maintaining stage is from the start moment of the bias stage to the start moment of the first light emission stage. Working modes of the display panel include a first mode and a second mode. The display brightness of the display panel in the first mode is different from the display brightness of the display panel in the second mode. The length of the bias maintaining stage in the first mode is different from the length of the bias maintaining stage in the second mode.

Display panel and device with bias maintaining stage duration according to brightness

A light-emission driving substrate includes: a substrate; a device layer disposed on the substrate, wherein the device layer comprises a plurality of first signal lines and second signal lines that are disposed in a light-emitting area, and includes a plurality of first connection terminals and second connection terminals that are disposed in a non-light-emitting area, each of the first connection terminals is electrically connected to an anode of the light-emitting element through the first signal line, and each of the second connection terminals is electrically connected to the cathode of a light-emitting element through the second signal line; and wherein a distance between at least one of the first connection terminals and the binding area is smaller than a distance between each of the second connection terminals and the binding area.

Light-emission driving substrate, light-emitting panel, and display device

Provided are a display panel, an integrated chip, and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module and a data writing module. The driving module is configured to supply a driving current to the light-emitting element. The data writing module is configured to write a data signal into the driving module. An operating mode of the display panel includes a first mode and a second mode. The brightness of the display panel in the first mode is greater than the brightness of the display panel in the second mode. In the first mode, the data signal corresponding to the light-emitting element is black state voltage G, and in the second mode, the data signal corresponding to the light-emitting element is black state voltage G, where G≠G.

Display panel, integrated chip, and display device

The present application discloses a display panel and its driving method, driving circuit and display device. The display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a first reset module configured to provide a reset signal for the light-emitting element under control of a first control signal; operation modes of the display panel includes a first mode and a second mode, a brightness of the display panel is L1 under the first mode, the brightness of the display panel is L2 under the second mode, and L1<L2; a refresh frequency of the first control signal is F1 under the first mode, the refresh frequency of the first control signal is F2 under the second mode, and F1<F2.

Display panel, method for driving display panel, driving circuit and display device

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data writing module, and a bias adjustment module. The driving module includes a driving transistor. The data writing module is configured to provide a data signal for the driving transistor. The bias adjustment module is configured to provide a bias adjustment signal for the driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. At least one of a source or a drain of the driving transistor is configured to receive the bias adjustment signal in the bias adjustment stage. An operating state of the pixel circuit includes a first mode and a second mode.

Provided are a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate and including driving circuits, LED chips located on side of the drive circuit layer facing away from the substrate and each electrically connected to a corresponding drive circuit, the drive circuit includes at least one first thin film transistor with a source and a drain located at first metal layer of the drive circuit layer and electrically connected to first electrode of corresponding LED chip, and at least part of edges of the display panel is provided with thermally conductive adhesive. The substrate is also provided with one or more layers of thermally conductive metal, at least one layer of thermally conductive metal extends to the edges of the display panel and is in contact with the thermally conductive adhesive.

Display panel and display device with enhanced thermal conductivity

A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, F1>F2>0. The pixel circuit includes a driving transistor, a first transistor, and a second transistor.

A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. The holding stage includes N stages arranged in sequence, N≥1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2.

A display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage. The first data adjustment stage includes Tfirst sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes mdata writing frames and nholding frames. The operation process of the pixel circuit further includes a first data refresh frequency Fand a second data refresh frequency F, and F<F. When the pixel circuit is operated at the first data refresh frequency F, the first data adjustment stage includes Tfirst sub-data adjustment stages set in sequence. When the pixel circuit is operated at the second data refresh frequency F, the first data adjustment stage includes Tfirst sub-data adjustment stages set in sequence. T>T

Display panel and display device with reduced screen flicker

A display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage, a second data adjustment stage, and a third data adjustment stage set in sequence. The first data adjustment stage includes Tfirst sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes mdata writing frames and nholding frames. The second data adjustment stage includes Tsecond sub-data adjustment stages set in sequence, each second sub-data adjustment stage includes mdata writing frames and nholding frames. The third data adjustment stage includes Tthird sub-data adjustment stages set in sequence, each third sub-data adjustment stage includes mdata writing frames and nholding stages set in sequence.

A display panel and a display device are provided. The display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage and a second data adjustment stage set in sequence. The first data adjustment stage includes T1 first sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes m1 data writing frames and n1 holding frames, T1≥1, m1≥0, n1≥0, and m1+n1≥1. The second data adjustment stage includes T2 second sub-data adjustment stages set in sequence, each second sub-data adjustment stage includes m2 data writing frames and n2 holding frames, T2≥1, m2≥0, n2≥0, and m2+n2≥1. T1>T2, T1/T2=(m2+n2)/(m1+n1).

Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

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Shanghai, China

Yuheng Zhang