Shanghai Ic R&d Center Co., Ltd

Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd

Yuhang Zhao

Xiaoxu Kang

Yong Wang

Jianxin Wen

Yan Chen

Wei Zhou

Chen Bo Li

Ling Shen

Shoumian Chen

Xi Zeng

Zheng Ren

Changming Pi

Shaojian Hu

The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

CMOS image sensor, image sensor unit and signal transmission methods therefor

The present invention provides an image sensor comprising a pixel array module composed of pixel groups, multiple switch control modules, a PFA, a pipelined ADC and a decode module. Each pixel group comprises multiple unit pixels which form at least one unit pixel. Each switch control module corresponds to a row of the pixel array module and includes a first transmission circuit and a second transmission circuit. The PGA process the data outputted by the first and second transmission circuits and the pipelined ADC performs A/D conversion to the data outputted by the PGA. The decode module controls the first and second transmission circuits of each row to alternately read and transmit the unit pixel data, and controls all the first and second transmission circuits to successively output the data of the unit pixels readout thereby to the PGA.

Image sensor and data tranmission method thereof

A capacitive silicon microphone comprises: a first dielectric layer sets on a substrate with a back cavity, a lower polar plate which is located over the back cavity, a first elastic member of which an inner edge is connected with the edge of the lower polar plate and an outer edge is located on the upper surface of the first dielectric layer, a second dielectric layer which is located on the outer edge of the first elastic member and right above the first dielectric layer, an upper polar plate which has a plurality of release holes and is formed above the lower polar plate with an air gap in between, a second elastic member of which an inner edge is connected with the edge of the upper polar plate and an outer edge is located on the upper surface of the second dielectric layer.

Capacitive silicon microphone and fabrication method thereof

A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Integrated circuit (IC) design method with enhanced circuit extraction models

The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.

Method for fabricating a carbon nanotube interconnection structure

A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element () and a multi-layer structure of a standard CMOS device arranged on the silicon substrate (). A deep groove () having a light-transmitting space therein is formed above the photosensitive element, a side wall of the deep groove is surrounded by a light reflection shielding layer () continuously arranged in a longitudinal direction to reflect the light incident on the light reflection shielding layer. The side wall of the deep groove is surrounded by metal interconnects, vias, contact holes and polysilicon in annular configurations, thus the incident light on the deep grove is substantially completely reflected, which avoids the optical crosstalk and effectively improves the optical resolution and sensitivity of the pixel and the performance and reliability of the chip.

Pixel structure of CMOS image sensor and manufacturing method thereof

A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

Copper interconnect structure and method for manufacturing the same

The present invention provides a multi-system multi-band RFID antenna, which comprises an on-chip antenna and at least one external antenna, wherein the on-chip antenna is arranged on RFID chip; the external antennas are arranged outside the RFID chip; and the RFID chip is provided with connection pads on the outer surface, wherein both the on-chip antenna and the external antennas are connected with the RFID chip through the connection pads. According to the multi-system multi-band RFID antenna of the present invention, the RFID chip can provide appropriate antennas for applications in different systems with different frequency bands, and can satisfactorily meet the need for RFID multi-system integration applications in the future.

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Shanghai, China

Yuhang Zhao