No. 24 Research Institute of China Electronic Technology Corporation

China Electronics Technology Group Corporation Chongqing Acoustic-optic-electronic Co., Ltd.

Yuhan Gao

Dongbing Fu

Guangbing Chen

Yuxin Wang

Zhengping Zhang

Lei Zhang

Can Zhu

Rongbin Hu

Jun Deng

Yonglu Wang

Lintao Liu

Haoming Du

Xiaozong Huang

Rongke Ye

The present invention relates to a CPT atomic clock servo control SoC, which includes a microprocessor, a photoelectric signal demodulation functional module, a temperature control loop functional module, a laser and microwave loop control functional module, a C field control functional module, and a bus bridge. The bus bridge is connected to a system bus and a peripheral bus, for connecting to buses with different speeds. The photoelectric signal demodulation functional module extracts power change information of a microwave and a laser. The temperature control loop functional module controls temperatures of an absorption cell and a laser tube. The laser and microwave loop control functional module implements laser frequency locking and microwave loop locking. The C field control functional module provides a stable C field for the absorption cell.

CPT atomic clock servo control SoC

The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.

Clock delay adjusting circuit based on edge addition and integrated chip thereof

Growing community of inventors

Chongqing, China

Yuhan Gao