Faraday Technology Corporation

Yuh-Kuang Tseng

Ming-Shih Yu

Ming-Dou Ker

Yuan-Wen Hsiao

Song-Rong Han

The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a bonding wire. The induction structure is coupled with the connection structure and lowers an effective capacitance between the bonding wire and the substrate.

Bonding pad structure disposed in semiconductor device and related method

A frequency comparator comparing frequencies of a first clock signal and a reference clock signal. The frequency comparator includes a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference clock signal, and outputs an up clock signal and a down clock signal. The pulse-width difference between the up clock signal and the down clock signal corresponds to the phase difference between the first clock signal and the reference clock signal. The comparison module compares the frequencies of the first clock signal and the reference clock signal based on how many times the pulse width of the up clock signal is larger or shorter than that of the down clock signal in a predetermined period.

Frequency comparator

A hysteresis current comparator includes a first current comparison unit, a second current comparison unit, and a control circuit connected to the two current comparison units. The first current comparison unit compares a first reference current with an input current and outputs a first voltage accordingly. The second current comparison unit compares a second reference current with the input current and outputs a second voltage accordingly. The control circuit generates an output voltage according to the voltages output by the two current comparison units, or generates an output voltage according to the voltages output by the two current comparison units and the output voltage of the control circuit at a former state.

Current comparator with hysteresis

A delay-locked loop device capable of anti-false-locking includes a voltage control delay circuit including a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupling to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupling to the phase detector for generating the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupling to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of each delay unit of the voltage control delay circuit.

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Tao-Yuan Hsien, Taiwan

Yuh-Kuang Tseng