Industrial Technology Research Institute

Yuh-Feng Hsu

Tsuhan Chen

Oscal Tzyh-Chiang Chen

Ming-Ting Sun

Zhi Zhou

Yeping Su

Ming-Tin Sun

Trista Pei-Chun Chen

Methods and systems for fast variable block-size motion estimation based on merging and splitting procedures for AVC video encoding are disclosed. The methods take advantage of the correlation of the Motion Vectors (MVs) of the different block-size modes to achieve a good computation reduction. Considering that the smaller the block-size difference between two block-sizes is, the more correlations between their MVs can be expected, the methods use a 8*8 block as an initial processing block to calculate prediction MVs. The prediction MVs are then used in predicting MVs for other block-sizes.

System and method for fast variable-size motion estimation

A fast non-iterative Global Motion Estimation (GME) algorithm is disclosed for estimating the perspective transform global motion parameters from the Motion Vectors (MV) obtained from the block matching process that includes grouping a plurality of motion vectors in the input video stream into a predetermined number of groups of motion vectors, calculating a set of global motion parameters from each of the predetermined groups of the motion vector, and processing the set of global motion parameters generated from the calculation to obtain a final estimation.

System and method for non-iterative global motion estimation

A method of error concealment that includes providing a first set of image data at a first time instant, providing a second set of image data at a second time instant, representing the first set of image data by a model of updating mixture of principal components (UMPC) to form a UMPC model having a plurality of components, receiving the second set of image data, wherein the second set of image data contains error-free data, and updating the UMPC model using the error-free data at the second time instant.

Method for video error concealment by updating statistics

A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

Growing community of inventors

Hsin-Chu, Taiwan

Yuh-Feng Hsu