Nippon Steel Corporation

Yugo Tomioka

Yasuo Sato

Shoichi Iwasa

Kenji Anzai

Toshio Wada

Yukihiro Okeda

A nonvolatile semiconductor memory device including a plurality of memory cells, and a method of making this memory device. The nonvolatile semiconductor memory device includes: a semiconductor substrate; an element-isolation structure formed in a surface of the semiconductor substrate and having at least two linear portions extending in a longitudinal direction to define at least one element region between them; and at least one of the memory cells formed in the element region and including: a pair of impurity diffusion layers formed in the surface of said semiconductor substrate along each of the linear portions and a floating gate of a conductive material formed in the element region so as to extend in a lateral direction crossing the longitudinal direction and to bridge the two linear portions, the floating gate including at least a first portion formed on the surface of the semiconductor substrate through a tunnel oxide film and a second portion formed on the surface of the semiconductor substrate through a gate oxide film so as to cover the first portion, the tunnel oxide film having a thickness smaller than that of the gate oxide film, wherein the first portion overlaps through the tunnel oxide film with one of the impurity diffusion layers at an overlapping area extending in the longitudinal direction and having a width equal to or less than 0.18 .mu.m measured in the lateral direction.

Nonvolatile semiconductor memory device and a method of making the same

A nonvolatile semiconductor storage device in which a composite gate of a floating gate memory cell transistor and a gate electrode of a peripheral MOS transistor are formed in the same lithography process and a manufacturing method thereof. A polycrystalline silicon film and an ONO film are formed on a well region through a gate oxide film and a tunnel oxide film. A polycrystalline silicon film is formed after removing the ONO film in the right region. A floating gate and a control gate of the memory cell transistor and a gate electrode of the select transistor are formed with photoresist as a mask. Thereafter, ions of impurities are implanted and diffused in a transverse direction, thereby to form an impurity diffused layer. With this, since the impurity diffused layer is formed by transverse diffusion of impurities after the tunnel oxide film is formed, it is possible to prevent deterioration of the film quality of the tunnel oxide film.

Nonvolatile semiconductor storage device and method of manufacturing

A non-volatile semiconductor memory unit comprises a memory cell having a semiconductor substrate, a control gate formed over the semiconductor substrate, an electric charge accumulative layer formed between the semiconductor substrate and the control gate, and a source and drain, both formed in the semiconductor substrate. The memory cell stores N-valued data (N being an integer more than 3) by accumulating an electric charge in the electric charge accumulative layer. A detector is provided for detecting a storage state before data rewrite of the memory cell. A comparison circuit compares the storage state before data rewrite, with a storage state after data rewrite to produce a difference therebetween. A rewrite circuit is included for rewriting the storage state of the memory cell by applying N-1 levels of predetermined voltages to the source, the drain and control gate of the memory cell, respectively, in accordance with the produced difference.

Multi-value level type non-volatile semiconductor memory unit and method

A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of spaced field-shield isolation structures formed on a surface of the substrate and extending parallelly in a first direction to provide element-forming regions at spaces between every adjacent two of the field-shield element isolation layers, a pair of impurity diffusion layers of a second conductivity type different from the first conductivity type formed in the surface of the substrate at portions adjacent opposite sides of each of the element-forming regions, a plurality of spaced lateral regions defined on the surface of the substrate and extending parallelly in a second direction intersecting with the first direction; and a plurality of discrete gate electrodes formed on the surface of the substrate at portions corresponding to intersections of the lateral and element-forming regions, respectively, in electrically insulated relationship with the substrate, the gate electrodes being aligned along the lateral regions. The semiconductor elements are formed at the intersections, respectively, each semiconductor element having a pair of portions of the impurity diffusion layers disposed at one of the intersection, and a channel region is formed between the portions of the diffusion layers and one of the gate electrodes formed at the one intersection. Also a method of making the semiconductor device includes respective steps of forming the above components constituting the semiconductor device.

Semiconductor device having field-shield isolation structures and a

A non-volatile semiconductor memory device comprises a semiconductor substrate, a shield gate electrode formed over a device isolation region of the semiconductor substrate through a shield gate insulating film, a floating gate electrode formed over a device region of the semiconductor substrate through a tunnel insulating film, the device region lying adjacent to the device isolation region and a part of the floating gate electrode overlapping the device isolation region so as to form a gap region therebetween, and a control gate electrode formed over the floating gate electrode through an oxide/nitride/oxide (ONO) film and formed over the shield gate electrode through a shield cap insulating film such that a part of the control gate electrode extends into the gap region.

Non-volatile semiconductor memory device with improved rewrite speed

An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Electrically alterable n-bit per cell non-volatile memory with reference

A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region. Each reference cell has the same electrical characteristic as the memory cell, with the method including:

Method of writing into non-volatile semiconductor memory

A part of a polycrystalline silicon film forming a grounding line in a memory cell of a high-resistance load type SRAM, located immediately below a contact hole for connection between a polysilicon power supply line part and an aluminum power supply line part, is separated and isolated from the remaining part of the polycrystalline silicon film to form an island-like part. The contact hole extends through an interlayer insulating film below the aluminum power supply line part, the polysilicon power supply line part and another interlayer insulating film above the island part, and reaches the island part, whereby the aluminum power supply line part contacts even the island part through the contact hole. The island part also contacts the polysilicon power supply line part through another contact hole, whereby low-resistance contact can be obtained between the aluminum and polysilicon power supply line parts through the island part. Since the contact hole can be provided at a position above a grounding line, the area of the cell can be reduced. In this case, even when the contact hole reaches the polycrystalline silicon film of the grounding line due to difficulties in its etching control, undesirable short-circuiting can be avoided between the grounding and power supply lines.

Semiconductor device having conducting layers connected through contact

A semiconductor memory having a memory cell including a stacked capacitor in which a lower electrode contacting one of two diffusion regions of an access transistor is formed in the form of two layers. It is preferable that impurities having a smaller diffusion coefficient, or arsenic is introduced into a first layer of the lower electrode contacting the diffusion region, and impurities having a larger diffusion coefficient, or phosphorus is introduced into a second layer of the lower electrode contacting capacitor dielectric film. Since a diffusion coefficient of arsenic is small, it is possible to prevent the junction of the diffusion region from becoming deep and on the other hand since phosphorus is introduced into the second polycrystalline Si film contacting the capacitor dielectric film, it is possible to prevent the degradation of the film quality of the capacitor dielectric film.

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Tokyo, Japan

Yugo Tomioka