Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Other

Hitachi Engineering Co., Ltd.

Renesas Technology Corp.

Yugo Kashiwagi

Keiichi Kurakazu

Mitsuru Watabe

Shiro Baba

Yasushi Akao

Kouki Noguchi

Takanaga Yamazaki

Shumpei Kawasaki

Toshimasa Kihara

Takashi Tsukamoto

Shigeki Masumura

Masahiro Kainaga

Kaoru Fukada

Eiji Sakakibara

Yoichi Asano

Katsuhiko Ishida

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Keisuke Toyama

Tan Watanabe

Shigeki Morinaga

Norio Nakagawa

Hiroyuki Kida

Tetsuaki Nakamikawa

Masahisa Narita

Junichi Tatezaki

Hisashi Kaziwara

Takeshi Asai

Shunpei Kawasaki

Tohru Nojiri

Hiroshi Yajima

Thoru Nojiri

Shinichi Yoshioka

Fumio Arakawa

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Branch instruction having different field lengths for unconditional and conditional displacements

Microcomputer having variable bit width area for displacement

Central processing unit having instruction queue of 32-bit length

Microcomputer having variable bit width area for displacement and

A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Division circuit and the division method thereof

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

Microcomputer having 16 bit fixed length instruction format

An executable program is stored in compressed form in a ROM, from which compressed program data is fetched to be expanded by an expandor to a pre-compression form. The expanded data is then decoded by an instruction decoder for execution. This novel setup reduces a memory usage amount in main storage including the ROM. If a branch instruction appears, a controller converts a pre-compression branch destination address to a corresponding post-compression branch destination address and sets a value thereof to a program counter.

Microcomputer executing compressed program and generating compressed

System for obtaining strict solution in accordance with accuracy of

In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating the main memory is provided in the same instruction.

RISC system with instructions which include register area and

A compiler incorporates obtained information for controlling the data-processor hardware, such as the position of the branch destination of a branch instruction and the used states of registers into object codes (NOP instruction) including a no-operation instruction code to post it to the data processor. The data processor is so constituted as to effectively use the data-processor resource not practically used by the no-operation instruction code and reflect the hardware control information included in the object code on data processing.

Data processor and method utilizing coded no-operation instructions

Growing community of inventors

Koganei, Japan

Yugo Kashiwagi