Intel Corporation

Yufu Li

Xiaohua Cai

Rahul Khanna

Murugasamy K Nachimuthu

Jian Tang

Vincent J Zimmer

Tao Xu

Lei Zhu

Shijie Liu

Peng Wang

Xiaoguo Liang

Ping Wu

James W Edwards

Abdul M Bailey

Xiang Ma

Zhijun Liu

Ye Li

Di Tang

Xiaohu Zhou

Geng Tian

Koo Heng Daniel Aw

Fumin Lu

Wenson Lin

Yanxin Zhao

A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

Method and system for error check and scrub error data collection and reporting for a memory device

Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.

Remote traffic performance on cluster-aware processors

Methods, apparatus, and system to compress a data file to form a compressed data file. The data file may be used to configure control of hardware, such as peripheral hardware. The compressed data file may be stored locally or transmitted to another computer device. The compressed data file may be stored in a flash memory. The compressed data file may require less space in flash memory components, relative to flash memory suitable to hold the (original, pre-compressed) data file. Compression and/or decompression may be performed by, for example, a flash memory controller. The compressed data file may be decompressed dynamically, on an as-needed basis, to provide code for execution by a processor and/or to configure a computer device to use hardware or other components. Other software and hardware components do not need to be aware that the data file is compressed in the flash memory.

Flash data compression decompression method and apparatus

Methods and apparatus to improve modification of system routing information in link based systems are described. In one embodiment, entries in a first table (storing data corresponding to routing paths between a plurality of components prior to a hot-plug event) and a second table (storing data corresponding to routing paths between the plurality of components after a hot-plug event) may be compared to determine which corresponding routing registers are to be modified in response to the hot-plug event. Other embodiments are also disclosed.

Modifying system routing information in link based systems

A system comprises a plurality of processor cores. The processor cores may comprise one or more application processor (AP) cores and a boot strap processor (BSP) core. A basic input/output system (BIOS) comprises an I/O device module to call a stall function in response to an I/O operation, a power management module that couples to the I/O device and a timer module that couples to the power management module. The power management module is to adjust a timer period of the timer module based on a stall delay of the stall function. The power management module may hook the stall function and compare the stall delay with a predetermined threshold and set the timer period to the stall delay in response to determining that the stall delay is longer. The power management module may put the BSP in a sleep mode during the timer period to save power.

System and method for power management using a basic input output system

Improved reliability, availability, and serviceability (RAS) is provided by an extensible and flexible firmware architecture. The architecture provides management for events, where an event is a response to an imminent failure of or capacity change requirement applicable to a component of the system. In response to an event, control of a system is transferred from an operating system to the firmware manager. The manager identifies an action that is specified by the event. Based on the action, the firmware manager selects a firmware handler from a plurality of firmware handlers. The firmware manager dispatches the selected firmware handler to perform the specified action. The firmware manager and the dispatched firmware handler exchange system-independent information regarding the event. The firmware manager also manages time-slices for the performance of the specified action by the dispatched firmware handler.

Extensible and flexible firmware architecture for reliability, availability, serviceability features

A spanning tree is assigned to a processing node for each processing node in a point-to-point network that connects a plurality of processing nodes. The spanning tree uses the processing nodes as vertices and links of the network as edges. Each processing node includes input snoop ports that can be configured as either terminating or forwarding. According to the assigned spanning trees and the configuration of the input snoop ports, the network routes snoop messages efficiently and without conflicts.

Optimized cache consistency algorithm in a point-to-point interconnected multiple processor system

Methods and arrangements for remapping the map between logical space and physical space in non-volatile storage are described. Embodiments include transformations, code, state machines or other logic to divide the non-volatile storage of the computing device into two portions, a fixed portion and a floating portion. The embodiments may also include remapping in system firmware of the computing device the current map from logical space to physical space of the floating portion of the non-volatile storage. The embodiments may also include storing the revised map. The embodiments may also include using the revised map to access the floating portion of the non-volatile storage.

Methods and arrangements to remap non-volatile storage

In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.

Dynamically discovering a system topology

Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor ('SBSP') to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

System information synchronization in a links-based multi-processor system

A link based system including a plurality of processors is reset when transitioning from a slower speed to a higher speed mode during a booting process. One processor may coordinate the simultaneous establishment of link resetting of a plurality of other processors. In one embodiment, the processors may operate beginning with the farthest processor to reset their local links. Each processor sets its local links and if it determines, based on the speed of the link that the link has already been reset, it moves on to the next link.

Parallel link reset in link based system

Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.

Methods and apparatus to change a configuration of a processor system

When a processing system boots, an image loader may determine whether a portable executable (PE) image for a platform firmware runtime service includes a discardable section. The image loader may load part of the PE image into runtime memory to be used by the platform firmware. In response to determining that the PE image includes a discardable section, the image loader may omit at least part of the discardable section when loading the PE image into the runtime memory. Instead, the image loader may load the discardable section into boot-time memory. In another embodiment, the image loader may pre-allocate an area of runtime memory for PE images, and may load sections from multiple PE images into the pre-allocated area. Also, the image loader may use an alignment granularity that is smaller than the page size when loading the PE images into the pre-allocated area. Other embodiments are described and claimed.

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Shanghai, China

Yufu Li