Cadence Design Systems, Inc.

Sierra Design Automation, Inc.

Yufeng Luo

Pinhong Chen

Miao Liu

Prasanna V Srinivas

Richard M Chou

Liqun Deng

Shankar Krishnamoorthy

Chin-Chih Chang

Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.

Concurrent optimization of 3D-IC with asymmetrical routing layers

A method and apparatus is described which allows efficient optimization of integrated circuit designs. By performing a global analysis of the circuit and identifying bottleneck nodes, optimization focuses on the nodes most likely to generate the highest return on investment and those that have the highest room for improvement. The identification of bottleneck nodes is seamlessly integrated into the timing analysis of the circuit design. Nodes are given a bottleneck number, which represents how important they are in meeting the objective function. By optimizing in order of highest bottleneck number, the optimization process converges quickly and will not get side-tracked by paths that cannot be improved.

Method and apparatus for optimization of digital integrated circuits using detection of bottlenecks

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San Jose, CA, United States of America

Yufeng Luo