Shanghai Biren Technology Co., Ltd

YuFei Zhang

Zhou Hong

ChengKun Sun

Wei Zhang

Tong Sun

ChengPing Luo

HaiChuan Wang

Qin Zheng

Zhu Liang

Min Gao

The embodiments of the disclosure relate to a computing device, a computing apparatus, and a method of warp accumulation and relate to the field of computers. The computing device includes a storage unit and an accumulation computing unit coupled to the storage unit. The accumulation computing unit is configured to receive, from a vector processing unit coupled to the computing device, a first warp accumulation instruction, a plurality of first values corresponding to a warp lane number, and a first storage address; generate a current accumulation result based on the plurality of first values in response to the first warp accumulation instruction; and store the current accumulation result in the first storage address in the storage unit to be read by the vector processing unit. In this way, accumulation in a warp may be decoupled to dedicated hardware for processing, and overall accumulation performance may thus be significantly improved.

Computing device, computing apparatus and method of warp accumulation

A method for computing, a computing device, and a computer-readable storage medium are provided. The method includes determining a first pixel block in a cache. The first pixel block is composed of a 2m row×2n column pixel matrix and includes original pixel data and pixel data related to the original pixel data. The first pixel block is read from the cache. At least part of the pixel data related to the original pixel data is used for padding related to the original pixel data. The original pixel data includes pixel data from the (n+1)column to the 2column in the (m+1)row to the 2row in the 2row×2 n column pixel matrix. When reading data from the cache, pixel data that needs to be obtained after insert-zero and padding operations on the original pixel data in back propagation can be read at one time.

Method for computing, computing device, and computer-readable storage medium

An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Interconnection device

The present disclosure relates to a method for computing, computing device and computer-readable storage medium. The method includes: determining a pixel block set in a cache, a first pixel block in the pixel block set comprising an m×n pixel matrix having a first padding setting related to the original pixel data, the m and n being positive integers; and storing the determined pixel block set in a buffer to enable a second pixel block to be read from the buffer based on the buffer initial address of the first pixel block and an address offset associated with the second pixel block, wherein the second pixel block has a second padding setting related to the original pixel data, and the first padding setting and the second padding setting have the same offset amount in a first direction relative to the original pixel data.

Method, computing device and computer readable storage medium for computing

The embodiments of the disclosure relate to a computing device, a computing equipment, and a programmable scheduling method for data loading and execution, and relate to the field of computer. The computing device is coupled to a first computing core and a first memory. The computing device includes a scratchpad memory, a second computing core, a first hardware queue, a second hardware queue and a synchronization unit. The second computing core is configured for acceleration in a specific field. The first hardware queue receives a load request from the first computing core. The second hardware queue receives an execution request from the first computing core. The synchronization unit configured to make the triggering of the load request and the execution request to cooperate with each other. In this manner, flexibility, throughput, and overall performance can be enhanced.

Computing device, computing equipment and programmable scheduling method

Information processing method, interconnection device and computer-readable storage medium

The invention relates to an apparatus for vector computing incorporating with matrix multiply and accumulation (MMA) calculation. The apparatus includes a streaming multiprocessor (SM), and a block selector. The register space is divided into physical blocks, each of which includes register groups, and a general matrix multiply (GEMM) calculation unit. The SM includes a general-purpose register (GPR), and the GEMM calculation unit includes an instruction queue and a arithmetic logical unit (ALU). The ALU coupled to the GPR is arranged operably to perform MMA calculation according to a GEMM instruction stored in the instruction queue, and store a calculation result in the GPR.

Apparatus and method for vector computing incorporating with matrix multiply and accumulation calculation

The embodiments of the disclosure relate to a computing device and a method for loading data. According to the method, the first processing unit sends a first instruction to the NMP unit. The first instruction includes a first address, a plurality of second addresses, and an operation type. In response to the first instruction, the NMP unit performs operations associated with the operation type on multiple data items on the multiple second addresses of the first memory, so as to generate the operation result. The NMP unit stores the operation result to the first address of the first memory. The first processing unit issues a flush instruction to make the operation result on the first address visible to the first processing unit. The first processing unit issues a read instruction to read the operation result on the first address to the first processing unit.

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Shanghai, China

YuFei Zhang