Texas Instruments Corporation

Yufei Xiong

Hong Yang

Yunlong Liu

Zachary K Lee

Jianxin Liu

Seetharaman Sridhar

Peng Hu

Ho Lin

Sheng Zou

Wei Tang

Christopher Boguslaw Kocon

Hideaki Kawahara

Michael F Chisholm

Qiuling Jia

Tianping Lv

Tian Ping Lv

Qiu Ling Jia

In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Method of fabricating a tungsten plug in a semiconductor device

In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

Transistor device with sinker contacts and methods for manufacturing the same

A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Power MOSFET with metal filled deep sinker contact for CSP

An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050&#xb0; C. to 1250&#xb0; C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050&#xb0; C. to 1250&#xb0; C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050&#xb0; C. to 1250&#xb0; C.

High quality deep trench oxide

An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Low resistance sinker contact

A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Field effect transistor and method of making

A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

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Chengdu, China

Yufei Xiong